Abstract: Solid-state shift register circuits, which have right and left shift capability and asynchronous set and clear, and asynchronous and synchronous parallel load capability are formed using a modified form of emitter function logic. These multicontrol shift register circuits achieve relatively high speed operation and have relatively low power dissipation, while requiring only a modest amount of silicon for implementation.

Abstract: An EFL D-type latch employing an EFL storage cell (17) controlled by a two-level tree of differential transistor pairs (12, 14 and 32, 34). Also described are counter cells, up counters, down counters and up/down counters, including binary, hexadecimal and BCD types, which can be formed from master/slave combinations of D-type and D-type latches. Examples of specific three-level and four-level EFL realizations of the counter cells are also described.

Abstract: A logic gate is formed as a full 3-EFL circuit including a full two-level ECL current switch tree and an EFL stage made up of input and output multiemitter transistors. By appropriate connections, the logic gate may be used for a variety of circuits including a 4:1 multiplexer and a comparator of two three-digit binary numbers. The logic gate advantageously is formed in a silicon chip which includes an array of cells each consisting essentially of nine single-emitter transistors, two four-emitter transistors and a number, advantageously nine, of resistors.

Abstract: An EFL J-K flip-flop circuit is provided in which feedback of only the true output Q of the slave latch to the input of the master section is required. The circuit in one embodiment includes a slave D-type latch comprising an EFL latch circuit combined with a one level current steering network, a master section comprising an EFL latch circuit combined with a two level current steering network, and an ECL inverter for complementing the K input signal to provide a K signal for the master section. All input combinational logic in the master section, including the complementing of the Q feedback signal, takes place in one emitter coupled transistor pair in the second level of the current steering network and at two input emitters of the master section EFL latch circuit. In an alternative embodiment, the ECL inverter is replaced by a third level current switch in the master section.