Patents by Inventor Robert J. Simpson
Robert J. Simpson has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9804995Abstract: This disclosure describes techniques for extending the architecture of a general purpose graphics processing unit (GPGPU) with parallel processing units to allow efficient processing of pipeline-based applications. The techniques include configuring local memory buffers connected to parallel processing units operating as stages of a processing pipeline to hold data for transfer between the parallel processing units. The local memory buffers allow on-chip, low-power, direct data transfer between the parallel processing units. The local memory buffers may include hardware-based data flow control mechanisms to enable transfer of data between the parallel processing units. In this way, data may be passed directly from one parallel processing unit to the next parallel processing unit in the processing pipeline via the local memory buffers, in effect transforming the parallel processing units into a series of pipeline stages.Type: GrantFiled: January 14, 2011Date of Patent: October 31, 2017Assignee: QUALCOMM IncorporatedInventors: Alexei V. Bourd, Andrew Gruber, Aleksandra L. Krstic, Robert J. Simpson, Colin Sharp, Chun Yu
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Patent number: 8941655Abstract: The example techniques described in this disclosure may be directed to interaction between a graphics processing unit (GPU) and a system memory. For example, the GPU may include a memory copy engine that handles tasks related to accessing data that is stored or is to be stored in the system memory. In addition, in some examples, the memory copy engine may perform additional tasks such as modification tasks to increase the performance of the GPU.Type: GrantFiled: September 7, 2011Date of Patent: January 27, 2015Assignee: QUALCOMM IncorporatedInventors: Petri Olavi Nordlund, Jukka-Pekka Arvo, Robert J. Simpson
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Patent number: 8842122Abstract: Aspects of the disclosure relate to a method of controlling a graphics processing unit. In an example, the method includes receiving one or more tasks from a host processor, and scheduling, independently from the host processor, the one or more tasks to be selectively executed by a shader processor and one or more fixed function hardware units, wherein the shader processor is configured to execute a plurality of instructions in parallel, and the one or more fixed function hardware units are configured to render graphics data.Type: GrantFiled: December 15, 2011Date of Patent: September 23, 2014Assignee: QUALCOMM IncorporatedInventors: Petri Olavi Nordlund, Jukka-Pekka Arvo, Robert J. Simpson
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Publication number: 20130155080Abstract: Aspects of the disclosure relate to a method of controlling a graphics processing unit. In an example, the method includes receiving one or more tasks from a host processor, and scheduling, independently from the host processor, the one or more tasks to be selectively executed by a shader processor and one or more fixed function hardware units, wherein the shader processor is configured to execute a plurality of instructions in parallel, and the one or more fixed function hardware units are configured to render graphics data.Type: ApplicationFiled: December 15, 2011Publication date: June 20, 2013Applicant: QUALCOMM INCORPORATEDInventors: Petri Olavi Nordlund, Jukka-Pekka Arvo, Robert J. Simpson
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Publication number: 20130057562Abstract: The example techniques described in this disclosure may be directed to interaction between a graphics processing unit (GPU) and a system memory. For example, the GPU may include a memory copy engine that handles tasks related to accessing data that is stored or is to be stored in the system memory. In addition, in some examples, the memory copy engine may perform additional tasks such as modification tasks to increase the performance of the GPU.Type: ApplicationFiled: September 7, 2011Publication date: March 7, 2013Applicant: QUALCOMM IncorporatedInventors: Petri Olavi Nordlund, Jukka-Pekka Arvo, Robert J. Simpson
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Publication number: 20120185671Abstract: This disclosure describes techniques for extending the architecture of a general purpose graphics processing unit (GPGPU) with parallel processing units to allow efficient processing of pipeline-based applications. The techniques include configuring local memory buffers connected to parallel processing units operating as stages of a processing pipeline to hold data for transfer between the parallel processing units. The local memory buffers allow on-chip, low-power, direct data transfer between the parallel processing units. The local memory buffers may include hardware-based data flow control mechanisms to enable transfer of data between the parallel processing units. In this way, data may be passed directly from one parallel processing unit to the next parallel processing unit in the processing pipeline via the local memory buffers, in effect transforming the parallel processing units into a series of pipeline stages.Type: ApplicationFiled: January 14, 2011Publication date: July 19, 2012Applicant: Qualcomm IncorporatedInventors: Alexei V. Bourd, Andrew Gruber, Aleksandra L. Krstic, Robert J. Simpson, Colin Sharp, Chun Yu
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Patent number: 5389830Abstract: There is described clock generation circuitry comprising: a plurality of sequentially connected delay devices, a first one of which is coupled to receive the first clock signal, each delay device being operable to produce a trigger signal and an output signal at a predetermined time after receiving a trigger signal from the previously connected delay device; control circuitry common to said delay devices for controlling said predetermined time interval; and output circuitry coupled to receive the output signals of the delay devices to produce therefrom said second clock signal.Type: GrantFiled: August 24, 1992Date of Patent: February 14, 1995Assignee: Inmos LimitedInventors: Keith Buckingham, Robert J. Simpson
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Patent number: 5345449Abstract: In an integrated circuit, a multiplexor receives incoming data at a first rate and is controllable by a high rate clock signal to output that data serially at a second, higher rate. A processing device receives the data from the multiplexor at the higher rate and is controllable by a high rate clock signal to process that data. Clock generation circuitry receives a first clock signal at the first rate and produces the high rate signal for the processing device and the multiplexor. Clock generation circuitry includes sequentially connected delay devices, one connected to receive the first clock signal. Each delay device produces a trigger signal and an output signal a predetermined time after receiving the trigger signal from the previous delay device. A control circuit is common to the delay devices for controlling the predetermined time interval. An output circuit receives the output signals of the delay devices and produces the high rate clock signal.Type: GrantFiled: February 25, 1993Date of Patent: September 6, 1994Assignee: Inmos LimitedInventors: Keith Buckingham, Robert J. Simpson
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Patent number: 5341371Abstract: A communication interface for interconnecting a computer with at least one other device has a link output circuit and a link input circuit. A link output on one device is connected to a link input on another device by a data line and a parallel strobe line. Data is transmitted on the data line in serial bit strings forming a succession of tokens of predetermined lengths. Signal transitions are provided on the parallel strobe line where no signal transition occurs on the data line. Each token includes a bit indicating the length of the token and a parity bit providing a check on bits in a preceding token.Type: GrantFiled: May 24, 1991Date of Patent: August 23, 1994Assignee: Inmos LimitedInventor: Robert J. Simpson
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Patent number: 5243597Abstract: An integrated circuit including a multiplexor connected to receive incoming data at a first rate and controllable by a high rate clock signal to output that data serially at a second, higher rate; a processing device coupled to receive data output from the multiplexor at the higher rate and controllable by a high rate clock signal to process that data; and clock generation circuitry connected to receive a first clock signal at said first rate and operable to produce therefrom said high rate clock signal to be supplied to the processing device and to the multiplexor.Type: GrantFiled: June 22, 1990Date of Patent: September 7, 1993Assignee: Inmos LimitedInventors: Keith Buckingham, Robert J. Simpson