Abstract: A method of determining a physical location for an address. The method includes receiving from a first global positioning system on a vehicle a first set of global positioning data indicative of a vehicle location. The method may also receive from a second global positioning system on a portable electronic device a second set of global positioning data indicative of a portable electronic device location. The method may also receive a set of location metadata associated with a picture. The method determines a residence location from the first set of global positioning data, the second set of global positioning data, or the set of location metadata. The method then associates the physical location to the address.

Abstract: A fire suppressing insulation. This insulation will create a barrier that blocks a fire to protect a structure from damage and will assist in suppressing the fire. Also, a fire suppression system including two walls, such as an interior wall and an exterior wall or two interior walls. The walls are spaced apart from each other by a divider to define an interior volume. At least a portion of the interior volume includes fire suppressing insulation that will form a fire suppressing intumescent barrier between the walls when exposed to the heat of a fire.

Abstract: Systems and methods of the present disclosure include at least one building component detection sensor device configured to be deployed within (or proximate to) a building comprised of a plurality of building components. The at least one building component detection sensor device is configured to detect data relating to at least one building component of the plurality of building components. In addition, a building component property determination system includes a processor configured to execute instructions stored in memory to determine one or more properties of the at least one building component based at least in part on the data detected by the at least one building component detection sensor device.

Abstract: The present invention relates generally to biointerface membranes utilized with implantable devices, such as devices for the detection of analyte concentrations in a biological sample. More particularly, the invention relates to novel biointerface membranes, to devices and implantable devices including these membranes, methods for forming the biointerface membranes on or around the implantable devices, and to methods for monitoring glucose levels in a biological fluid sample using an implantable analyte detection device.

Abstract: A method includes projecting light to obtain a reference measurement using a first photoresistor; collecting dust on a platform during a collection time interval; and projecting light across the platform to obtain a dust measurement using the first photoresistor or a second photoresistor.

Abstract: A transcutaneous sensor device configured for continuously measuring analyte concentrations in a host is provided. In some embodiments, the transcutaneous sensor device 100 comprises an in vivo portion 160 configured for insertion under the skin 180 of the host and an ex vivo portion 170 configured to remain above the surface of the skin 180 of the host after sensor insertion of the in vivo portion. The in vivo portion may comprise a tissue piercing element 110 configured for piercing the skin 180 of the host and a sensor body 120 comprising a material or support member 130 that provides sufficient column strength to allow the sensor body to be pushable in a host tissue without substantial buckling. The ex vivo portion 170 may be configured to comprise (or operably connect to) a sensor electronics unit and may comprise a mounting unit 150. Also described here are various configurations of the sensor body and the tissue piercing element that may be used to protect the membrane of the sensor body.

Abstract: A system for dispensing flame retardant foam on the exterior of a structure. The structure has an opening that enables distribution of flame retardant foam onto the roof. The system includes a foam distribution system having a foam expansion chamber and a roof plenum for delivery through the roof opening. Foam solution and compressed air are combined in a conduit and supplied to the foam expansion chamber. The structure may have at least one wall. In that case, the system may have a wall plenum for delivery of flame retardant foam from the foam expansion chamber through a first wall-associated opening. Each such wall will have an opening associated with the wall that enables distribution of flame retardant foam onto that wall.

Abstract: A system may include a router that may receive a plurality of data packets from one or more devices that communicatively couples to the router. The system may also include at least one processor that identifies an identity of a device based on a data packet received by the router from the device, generate an insurance policy that includes the device in response to identifying the identity of the device, and sends a notification indicative of the insurance policy to a computing device in response to generating the insurance policy.

Abstract: Systems and methods of use involving sensors having a particle-containing domain are provided for continuous analyte measurement in a host. In some embodiments, a continuous analyte measurement system is configured to be wholly, transcutaneously, intravascularly or extracorporeally implanted.

Abstract: This disclosure describes techniques for extending the architecture of a general purpose graphics processing unit (GPGPU) with parallel processing units to allow efficient processing of pipeline-based applications. The techniques include configuring local memory buffers connected to parallel processing units operating as stages of a processing pipeline to hold data for transfer between the parallel processing units. The local memory buffers allow on-chip, low-power, direct data transfer between the parallel processing units. The local memory buffers may include hardware-based data flow control mechanisms to enable transfer of data between the parallel processing units. In this way, data may be passed directly from one parallel processing unit to the next parallel processing unit in the processing pipeline via the local memory buffers, in effect transforming the parallel processing units into a series of pipeline stages.

Abstract: The example techniques described in this disclosure may be directed to interaction between a graphics processing unit (GPU) and a system memory. For example, the GPU may include a memory copy engine that handles tasks related to accessing data that is stored or is to be stored in the system memory. In addition, in some examples, the memory copy engine may perform additional tasks such as modification tasks to increase the performance of the GPU.

Abstract: Aspects of the disclosure relate to a method of controlling a graphics processing unit. In an example, the method includes receiving one or more tasks from a host processor, and scheduling, independently from the host processor, the one or more tasks to be selectively executed by a shader processor and one or more fixed function hardware units, wherein the shader processor is configured to execute a plurality of instructions in parallel, and the one or more fixed function hardware units are configured to render graphics data.

Abstract: Aspects of the disclosure relate to a method of controlling a graphics processing unit. In an example, the method includes receiving one or more tasks from a host processor, and scheduling, independently from the host processor, the one or more tasks to be selectively executed by a shader processor and one or more fixed function hardware units, wherein the shader processor is configured to execute a plurality of instructions in parallel, and the one or more fixed function hardware units are configured to render graphics data.

Abstract: The example techniques described in this disclosure may be directed to interaction between a graphics processing unit (GPU) and a system memory. For example, the GPU may include a memory copy engine that handles tasks related to accessing data that is stored or is to be stored in the system memory. In addition, in some examples, the memory copy engine may perform additional tasks such as modification tasks to increase the performance of the GPU.

Abstract: This disclosure describes techniques for extending the architecture of a general purpose graphics processing unit (GPGPU) with parallel processing units to allow efficient processing of pipeline-based applications. The techniques include configuring local memory buffers connected to parallel processing units operating as stages of a processing pipeline to hold data for transfer between the parallel processing units. The local memory buffers allow on-chip, low-power, direct data transfer between the parallel processing units. The local memory buffers may include hardware-based data flow control mechanisms to enable transfer of data between the parallel processing units. In this way, data may be passed directly from one parallel processing unit to the next parallel processing unit in the processing pipeline via the local memory buffers, in effect transforming the parallel processing units into a series of pipeline stages.

Abstract: There is described clock generation circuitry comprising: a plurality of sequentially connected delay devices, a first one of which is coupled to receive the first clock signal, each delay device being operable to produce a trigger signal and an output signal at a predetermined time after receiving a trigger signal from the previously connected delay device; control circuitry common to said delay devices for controlling said predetermined time interval; and output circuitry coupled to receive the output signals of the delay devices to produce therefrom said second clock signal.

Abstract: In an integrated circuit, a multiplexor receives incoming data at a first rate and is controllable by a high rate clock signal to output that data serially at a second, higher rate. A processing device receives the data from the multiplexor at the higher rate and is controllable by a high rate clock signal to process that data. Clock generation circuitry receives a first clock signal at the first rate and produces the high rate signal for the processing device and the multiplexor. Clock generation circuitry includes sequentially connected delay devices, one connected to receive the first clock signal. Each delay device produces a trigger signal and an output signal a predetermined time after receiving the trigger signal from the previous delay device. A control circuit is common to the delay devices for controlling the predetermined time interval. An output circuit receives the output signals of the delay devices and produces the high rate clock signal.

Abstract: A communication interface for interconnecting a computer with at least one other device has a link output circuit and a link input circuit. A link output on one device is connected to a link input on another device by a data line and a parallel strobe line. Data is transmitted on the data line in serial bit strings forming a succession of tokens of predetermined lengths. Signal transitions are provided on the parallel strobe line where no signal transition occurs on the data line. Each token includes a bit indicating the length of the token and a parity bit providing a check on bits in a preceding token.

Abstract: An integrated circuit including a multiplexor connected to receive incoming data at a first rate and controllable by a high rate clock signal to output that data serially at a second, higher rate; a processing device coupled to receive data output from the multiplexor at the higher rate and controllable by a high rate clock signal to process that data; and clock generation circuitry connected to receive a first clock signal at said first rate and operable to produce therefrom said high rate clock signal to be supplied to the processing device and to the multiplexor.