Abstract: A method and apparatus for scan testing an array (20) in a data processing system (10). In one form, the present invention uses a scanning sense amplifier (22x) which can perform the three functions of a sense amplifier, a master test latch for scan testing, and a slave test latch for scan testing. Using one scanning sense amplifier (22x) to perform all three functions reduces the amount of circuitry required to scan test an array (20). The same stimulus is applied twice to the array (20); and half of the output data bits are scanned out during each application of the stimulus. One extra output data bit is also scanned out during each application of the stimulus. The end result is a reduction in the circuitry required to perform scan testing.

Abstract: A data processor microsequencer having a non-multiplexed internal address bus is provided. The microsequencer includes a nanoROM, for providing control information to an execution unit, an entry point PLA for decoding a macroinstruction address and providing an initial microinstruction address, and a microROM, for providing the next microinstruction address during instruction sequencing. The entry PLA accesses macroinstructions from an instruction pipeline, and decodes the macroinstructions, thereby providing an initial microinstruction address for the microroutine to perform the macroinstruction. The initial microinstruction address is temporarily stored in a microprogram counter latch (uPC) and provided to the microROM or the nanoROM for decoding. The microROM decodes the initial microinstruction address and provides N output bits which are routed directly into the PLA, and subsequently provided to the uPC.

Abstract: A data processor has a microcode memory which is reduced in size by sharing word locations having the same contents. When one of the shared word locations is addressed, a control signal is generated and coupled to a select circuit. The select circuit outputs a predetermined operand in place of the contents of the addressed shared word location which can contain a "do not care" operand value. Selective sharing or combining of the word locations is utilized when structuring the memory to optimize savings in circuit area.

Abstract: A data processing system (10) has a control selector (30) which has at least one conductor used for the common functions of shifting data and controling the generation of constants in an execution unit (26). A logic circuit (34) provides control signals to enable the control selector (30) to perform an information transfer, a shift operation, or a constant generation function. A plurality of constant signals enables a plurality of transistors (82, 114, 130, 84, 132, 86, 134) to generate a plurality of constant values. During an operation to shift data, a portion of the logic circuit (30) which generates a constant value is disabled by a Shift Disable signal. The conductors used to enable the control electrodes of the transistors during a constant generation function are used to shift data a predetermined number of bits when two shift signals are asserted.

Abstract: A data processor having a microsequencer which reduces power consumption selectively activates instruction decode units and a microcode sequence control memory unit. The microsequencer has an instruction decode unit implemented with a plurality of PLAs and also has a microcoded ROM for providing the next microaddress. The instruction decode unit outputs a next microaddress, a next-PLA field, and a ROM-or-PLA control bit. The control bit functions to minimize power in the data processor. The next-PLA field is latched and used to select a single decode unit when the next instruction decode is needed to activate a predetermined decode unit. Early macroinstruction branching can be performed in the data processor thereby improving performance.

Abstract: A data processor having a microsequencer which reduces power consumption selectively activates instruction decode units and a microcode sequence control memory unit. The microsequencer has an instruction decode unit implemented with a plurality of PLAs and also has a microcoded ROM for providing the next microaddress. The instruction decode unit outputs a next microaddress, a next-PLA field, and a ROM-or-PLA control bit. The control bit functions to minimize power in the data processor. The next-PLA field is latched and used to select a single decode unit when the next instruction decode is needed to activate a predetermined decode unit. Early macroinstruction branching can be performed in the data processor thereby improving performance.