Abstract: Concurrent servicing of a first cable of a cable pair while a second cable of the cable pair remains operational improves multi-processor computer system availability and serviceability. A pair of processing chips in different processing drawers may continue operation by way of the second cable while the first cable is degraded or serviced. Upon the servicing of the first cable, the serviced cable may transition to a fully operational state with no interruptions to the operations between the processing drawers by way of the second cable. Since cable faults are typically more common than processing chip or processing drawer faults, identification of cable faults and the ability to maintain operations of the processing drawers connected therewith is increasingly important.

Abstract: A computer system and a method implementing a remote access array are provided. A first drawer includes a first processor chip. A first main memory region is operatively connected to the first processor chip. A first non-addressable memory region is operatively connected to the first processor chip and includes the first remote access array. The first remote access array is configured to track data portions that are stored in the first main memory region and for which copies were created and sent to an external node. The first remote access array is backed up in the first main memory region. The first remote access array includes one or more entries and is configured to update all of the entries in response to a multi-drawer working partition being reduced to fit within the first drawer.

Abstract: Serialized broadcast command messaging in a distributed symmetric multiprocessing (SMP) system, including: sending a serial broadcast command from a home chip to a plurality of other chips comprising serial primary chip, wherein each chip of the plurality of other chips comprises a broadcast controller mapped to a home chip broadcast controller; assigning, by the serial primary chip, a tag to the serial broadcast command; sending, from the serial primary chip, to the home chip and a remainder of the plurality of other chips, the tag; and broadcasting, by the home chip and each chip of the plurality of other chips, the serial broadcast command in an order based on the tag of the serial broadcast command.

Abstract: Embodiments herein described a coherency protocol for a distributed computing topology that permits for large stalls on various interfaces. In one embodiment, the computing topology includes multiple boards which each contain multiple processors. When a particular core on a processor wants access to data that is not currently stored in its cache, the core can first initiate a request to search for the cache line in the caches for other cores on the same processor. If the cache line is not found, the cache coherency protocol permits the processor to then broadcast a request to the other processors on the same board. If a processor on the same board does not have the data, the processor can then broadcast the request to the other boards in the system. The processors in those boards can then search their caches to identify the data.

Abstract: A computer system and a method implementing a remote access array are provided. A first drawer may include a first processor chip. A first main memory region may be operatively connected to the first processor chip. A first non-addressable memory region may be operatively connected to the first processor chip and may include the first remote access array. The first remote access array may be configured to track data portions that are pulled from the first main memory region and that are sent to an external node. The first remote access array may be backed up in the first main memory region. The first remote access array may include one or more entries and may be configured to scrub all of the entries in response to a multi-drawer working partition being shrunk to fit within the first drawer.

Abstract: Concurrent servicing of a first cable of a cable pair while a second cable of the cable pair remains operational improves multi-processor computer system availability and serviceability. A pair of processing chips in different processing drawers may continue operation by way of the second cable while the first cable is degraded or serviced. Upon the servicing of the first cable, the serviced cable may transition to a fully operational state with no interruptions to the operations between the processing drawers by way of the second cable. Since cable faults are typically more common than processing chip or processing drawer faults, identification of cable faults and the ability to maintain operations of the processing drawers connected therewith is increasingly important.

Abstract: Embodiments herein described a coherency protocol for a distributed computing topology that permits for large stalls on various interfaces. In one embodiment, the computing topology includes multiple boards which each contain multiple processors. When a particular core on a processor wants access to data that is not currently stored in its cache, the core can first initiate a request to search for the cache line in the caches for other cores on the same processor. If the cache line is not found, the cache coherency protocol permits the processor to then broadcast a request to the other processors on the same board. If a processor on the same board does not have the data, the processor can then broadcast the request to the other boards in the system. The processors in those boards can then search their caches to identify the data.

Abstract: Castout handling in a distributed cache topology, including: detecting, by a first cache of a plurality of caches, a cache miss; providing, by the first cache to each other cache of the plurality of caches, a message comprising: data indicating a cache address corresponding to the cache miss; and data indicating a cache line to be evicted.

Abstract: Aspects of the invention include defining one or more processor units having a plurality of caches, each processor unit comprising a processor having at least one cache, and wherein each of the one or more processor units are coupled together by an interconnect fabric, for each of the plurality of caches, arranging a plurality of cache lines into one or more congruence classes, each congruence class comprises a chronology vector, arranging each cache in the plurality of caches into a cluster of caches based on a plurality of scope domains, determining a first cache line to evict based on the chronology vector, and determining a target cache for installing the first cache line based on a scope of the first cache line and a saturation metric associated with the target cache, wherein the scope of the first cache line is determined based on lateral persistence tag bits.

Abstract: Aspects of the invention include defining one or more processor units having a plurality of caches, each processor unit comprising a processor having at least one cache, and wherein each of the one or more processor units are coupled together by an interconnect fabric, for each of the plurality of caches, arranging a plurality of cache lines into one or more congruence classes, each congruence class comprises a chronology vector, arranging each cache in the plurality of caches into a cluster of caches based on a plurality of scope domains, determining a first cache line to evict based on the chronology vector, and determining a target cache for installing the first cache line based on a scope of the first cache line and a saturation metric associated with the target cache, wherein the scope of the first cache line is determined based on lateral persistence tag bits.

Abstract: Embodiments of the present invention are directed to a computer-implemented method for controller address contention assumption. A non-limiting example computer-implemented method includes a shared controller receiving a fetch request for data from a first requesting agent, the receiving via at least one intermediary controller. The shared controller performs an address compare using a memory address of the data.

Abstract: Embodiments of the present invention are directed to a computer-implemented method for controller address contention assumption. A non-limiting example computer-implemented method includes a shared controller receiving a fetch request for data from a first requesting agent, the receiving via at least one intermediary controller. The shared controller performs an address compare using a memory address of the data.

Abstract: A computer system includes a cache and processor. The cache includes a plurality of data compartments configured to store data. The data compartments are arranged as a plurality of data rows and a plurality of data columns. Each data row is defined by an addressable index. The processor is in signal communication with the cache, and is configured to operate in a full cache purge mode and a selective cache purge mode. In response to invoking one or both of the full cache purge mode and the selective cache purge mode, the processor performs a pipe pass on a selected addressable index to determine a number of valid compartments and a number of invalid compartments, and performs an eviction operation on the valid compartments while skipping the eviction operation on the invalid compartments.

Abstract: Embodiments of the present invention are directed to a computer-implemented method for controller address contention assumption. A non-limiting example computer-implemented method includes a shared controller receiving a fetch request for data from a first requesting agent, the receiving via at least one intermediary controller. The shared controller performs an address compare using a memory address of the data. In response to the memory address matching a memory address stored in the shared controller, the shared controller acknowledges the at least one intermediary controller's fetch request, wherein upon acknowledgement, the at least one intermediary controller resets. In response to release of the data by a second requesting agent, the shared controller transmits the data to the first requesting agent.

Abstract: Embodiments of the present invention are directed to a computer-implemented method for cache eviction. The method includes detecting a first data in a shared cache and a first cache in response to a request by a first processor. The first data is determined to have a mid-level cache eviction priority. A request is detected from a second processor for a same first data as requested by the first processor. However, in this instance, the second processor has indicated that the same first data has a low-level cache eviction priority. The first data is duplicated and loaded to a second cache, however, the data has a low-level cache eviction priority at the second cache.

Abstract: Embodiments of the present invention are directed to a computer-implemented method for controller address contention assumption. A non-limiting example computer-implemented method includes a shared controller receiving a fetch request for data from a first requesting agent, the receiving via at least one intermediary controller. The shared controller performs an address compare using a memory address of the data. In response to the memory address matching a memory address stored in the shared controller, the shared controller acknowledges the at least one intermediary controller's fetch request, wherein upon acknowledgement, the at least one intermediary controller resets. In response to release of the data by a second requesting agent, the shared controller transmits the data to the first requesting agent.

Abstract: Methods and systems for cache management are provided. Aspects include providing a drawer including a plurality of clusters, each of the plurality of clusters including a plurality of processor each having one or more cores, wherein each of the one or more cores shares a first cache memory, providing a second cache memory shared among the plurality of clusters, and receiving a cache line request from one of the one or more cores to the first cache memory, wherein the first cache memory sends a request to a memory controller to retrieve the cache line from a memory, store the cache line in the first cache memory, create a directory state associated with the cache line, and provide the directory state to the second cache memory to create a directory entry for the cache line.

Abstract: Methods and systems for secure storage protection for memory operations are provided. Aspects include providing a drawer comprising a plurality of clusters, each of the plurality of clusters comprising a plurality of processors, wherein each of the plurality of clusters share a first cache memory, providing a cluster shared cache integrated circuit to manage a second cache memory shared among the plurality of clusters, providing a system memory associated with each of the plurality of clusters, receiving, by a memory controller, a memory operation request from one of the plurality of processors, wherein the memory operation includes a store command, and wherein the memory controller is configured to perform the memory operation and atomically write a secure storage key for the memory operation with the store command of the memory operation.

Abstract: In one example implementation according to aspects of the present disclosure, a computer-implemented method for executing a load instruction with a timeout includes receiving, by a processing device, the load instruction. The method further includes attempting, by the processing device, to load a lock on a cache line of a memory. The method further includes determining, by the processing device, whether the timeout has expired prior to a successful loading of the lock on the cache line. The method further includes , responsive to determining that the timeout has expired, executing, by the processing device, another instruction instead of loading the lock on the cache line.

Abstract: Processing simultaneous data requests regardless of active request in the same addressable index of a cache. In response to the cache miss in the given congruence, if the number of other compartments in the given congruence class that have an active operation is less than a predetermined threshold, setting a Do Not Cast Out (DNCO) pending indication for each of the compartments that have an active operation in order to block access to each of the other compartments that have active operations and, if the number of other compartments in the given congruence class that have an active operation is not less than a predetermined threshold, blocking another cache miss from occurring in the compartments of the given congruence class by setting a congruence class block pending indication for the given congruence class in order to block access to each of the other compartments of the given congruence class.