Abstract: Topology of clusters of processors of a computer configuration, configured to support any of a plurality of cache coherency protocols, is discovered at initialization time to determine which one of the plurality of cache coherency protocols is to be used to handle coherency requests of the configuration.

Abstract: A computer system includes a cache and processor. The cache includes a plurality of data compartments configured to store data. The data compartments are arranged as a plurality of data rows and a plurality of data columns. Each data row is defined by an addressable index. The processor is in signal communication with the cache, and is configured to operate in a full cache purge mode and a selective cache purge mode. In response to invoking one or both of the full cache purge mode and the selective cache purge mode, the processor performs a pipe pass on a selected addressable index to determine a number of valid compartments and a number of invalid compartments, and performs an eviction operation on the valid compartments while skipping the eviction operation on the invalid compartments.

Abstract: Processing simultaneous data requests regardless of active request in the same addressable index of a cache. In response to the cache miss in the given congruence, if the number of other compartments in the given congruence class that have an active operation is less than a predetermined threshold, setting a Do Not Cast Out (DNCO) pending indication for each of the compartments that have an active operation in order to block access to each of the other compartments that have active operations and, if the number of other compartments in the given congruence class that have an active operation is not less than a predetermined threshold, blocking another cache miss from occurring in the compartments of the given congruence class by setting a congruence class block pending indication for the given congruence class in order to block access to each of the other compartments of the given congruence class.

Abstract: Speculative data return in parallel with an exclusive invalidate request. A requesting processor requests data from a shared cache. The data is owned by another processor. Based on the request, an invalidate request is sent to the other processor requesting the other processor to release ownership of the data. Concurrent to the invalidate request being sent to the other processor, the data is speculatively provided to the requesting processor.

Abstract: Methods and systems for secure storage protection for memory operations are provided. Aspects include providing a drawer comprising a plurality of clusters, each of the plurality of clusters comprising a plurality of processors, wherein each of the plurality of clusters share a first cache memory, providing a cluster shared cache integrated circuit to manage a second cache memory shared among the plurality of clusters, providing a system memory associated with each of the plurality of clusters, receiving, by a memory controller, a memory operation request from one of the plurality of processors, wherein the memory operation includes a store command, and wherein the memory controller is configured to perform the memory operation and atomically write a secure storage key for the memory operation with the store command of the memory operation.

Abstract: Methods and systems for cache management are provided. Aspects include providing a drawer including a plurality of clusters, each of the plurality of clusters including a plurality of processor each having one or more cores, wherein each of the one or more cores shares a first cache memory, providing a second cache memory shared among the plurality of clusters, and receiving a cache line request from one of the one or more cores to the first cache memory, wherein the first cache memory sends a request to a memory controller to retrieve the cache line from a memory, store the cache line in the first cache memory, create a directory state associated with the cache line, and provide the directory state to the second cache memory to create a directory entry for the cache line.

Abstract: Embodiments of the present invention are directed to a computer-implemented method for cache eviction. The method includes detecting a first data in a shared cache and a first cache in response to a request by a first processor. The first data is determined to have a mid-level cache eviction priority. A request is detected from a second processor for a same first data as requested by the first processor. However, in this instance, the second processor has indicated that the same first data has a low-level cache eviction priority. The first data is duplicated and loaded to a second cache, however, the data has a low-level cache eviction priority at the second cache.

Abstract: Speculative data return in parallel with an exclusive invalidate request. A requesting processor requests data from a shared cache. The data is owned by another processor. Based on the request, an invalidate request is sent to the other processor requesting the other processor to release ownership of the data. Concurrent to the invalidate request being sent to the other processor, the data is speculatively provided to the requesting processor.

Abstract: In an approach for purging an address range from a cache, a processor quiesces a computing system. Cache logic issues a command to purge a section of a cache to higher level memory, wherein the command comprises a starting storage address and a range of storage addresses to be purged. Responsive to each cache of the computing system activating the command, cache logic ends the quiesce of the computing system. Subsequent to ending the quiesce of the computing system, Cache logic purges storage addresses from the cache, based on the command, to the higher level memory.

Abstract: Embodiments of the present invention are directed to managing a shared high-level cache for dual clusters of fully connected integrated circuit multiprocessors. An example of a computer-implemented method includes: providing a drawer comprising a plurality of clusters, each of the plurality of clusters comprising a plurality of processors; providing a shared cache integrated circuit to manage a shared cache memory among the plurality of clusters; receiving, by the shared cache integrated circuit, an operation of one of a plurality of operation types from one of the plurality of processors; and processing, by the shared cache integrated circuit, the operation based at least in part on the operation type of the operation according to a set of rules for processing the operation type.

Abstract: Embodiments of the present invention are directed to managing a shared high-level cache for dual clusters of fully connected integrated circuit multiprocessors. An example of a computer-implemented method includes: providing a drawer comprising a plurality of clusters, each of the plurality of clusters comprising a plurality of processors; providing a shared cache integrated circuit to manage a shared cache memory among the plurality of clusters; receiving, by the shared cache integrated circuit, an operation of one of a plurality of operation types from one of the plurality of processors; and processing, by the shared cache integrated circuit, the operation based at least in part on the operation type of the operation according to a set of rules for processing the operation type.

Abstract: A system and method to transfer an ordered partial store of data from a controller to a memory subsystem receives the ordered partial store of data into a buffer of the controller. The method also includes issuing a preinstall command to the memory subsystem, wherein the preinstall command indicates that data from a number of addresses of memory corresponding with a target memory location be obtained in local memory of the memory subsystem along with ownership of the data for subsequent use. A query command is issued to the memory subsystem. The query command requests an indication from the memory subsystem that the memory subsystem is ready to receive and correctly serialize the ordered partial store of data. The ordered partial store of data is transferred from the controller to the memory subsystem.

Abstract: In an approach for purging an address range from a cache, a processor quiesces a computing system. Cache logic issues a command to purge a section of a cache to higher level memory, wherein the command comprises a starting storage address and a range of storage addresses to be purged. Responsive to each cache of the computing system activating the command, cache logic ends the quiesce of the computing system. Subsequent to ending the quiesce of the computing system, Cache logic purges storage addresses from the cache, based on the command, to the higher level memory.

Abstract: Topology of clusters of processors of a computer configuration, configured to support any of a plurality of cache coherency protocols, is discovered at initialization time to determine which one of the plurality of cache coherency protocols is to be used to handle coherency requests of the configuration.

Abstract: Topology of clusters of processors of a computer configuration, configured to support any of a plurality of cache coherency protocols, is discovered at initialization time to determine which one of the plurality of cache coherency protocols is to be used to handle coherency requests of the configuration.

Abstract: In an approach for purging an address range from a cache, a processor quiesces a computing system. Cache logic issues a command to purge a section of a cache to higher level memory, wherein the command comprises a starting storage address and a range of storage addresses to be purged. Responsive to each cache of the computing system activating the command, cache logic ends the quiesce of the computing system. Subsequent to ending the quiesce of the computing system, Cache logic purges storage addresses from the cache, based on the command, to the higher level memory.

Abstract: In an approach for purging an address range from a cache, a processor quiesces a computing system. Cache logic issues a command to purge a section of a cache to higher level memory, wherein the command comprises a starting storage address and a range of storage addresses to be purged. Responsive to each cache of the computing system activating the command, cache logic ends the quiesce of the computing system. Subsequent to ending the quiesce of the computing system, Cache logic purges storage addresses from the cache, based on the command, to the higher level memory.

Abstract: An aspect includes interlocking operations in an address-sliced cache system. A computer-implemented method includes determining whether a dynamic memory relocation operation is in process in the address-sliced cache system. Based on determining that the dynamic memory relocation operation is in process, a key operation is serialized to maintain a sequenced order of completion of the key operation across a plurality of slices and pipes in the address-sliced cache system. Based on determining that the dynamic memory relocation operation is not in process, a plurality of key operation requests is allowed to launch across two or more of the slices and pipes in parallel in the address-sliced cache system while ensuring that only one instance of the key operations is in process across all of the slices and pipes at a same time.

Abstract: Embodiments include methods, systems and computer program products method for maintaining ordered memory access with parallel access data streams associated with a distributed shared memory system. The computer-implemented method includes performing, by a first cache, a key check, the key check being associated with a first ordered data store. A first memory node signals that the first memory node is ready to begin pipelining of a second ordered data store into the first memory node to an input/output (I/O) controller. A second cache returns a key response to the first cache indicating that the pipelining of the second ordered data store can proceed. The first memory node sends a ready signal indicating that the first memory node is ready to continue pipelining of the second ordered data store into the first memory node to the I/O controller, wherein the ready signal is triggered by receipt of the key response.

Abstract: Topology of clusters of processors of a computer configuration, configured to support any of a plurality of cache coherency protocols, is discovered at initialization time to determine which one of the plurality of cache coherency protocols is to be used to handle coherency requests of the configuration.