Abstract: A dynamic address translation (DAT) mechanism which supports virtual memory pages of different sizes with minimal hardware and design impact. The dynamic look-aside table (DLAT) is modified to allow the addition of a second page size to system architecture. In one approach, the DLAT is divided into two sections, one for small (4KB) pages and one for large (1MB) pages. A steering table indicates whether the segment last contained 4KB pages or a 1MB page. As each segment is translated by the DAT mechanism, the page size (1MB or 4KB) contained in the segment is known, and this information is used to select the address bus used for indexing the DLAT. In an alternative approach, the DLAT is not divided into sections; rather, it can interchangeably hold/test/select either of the two different formats in any entry. The steering table dynamically changes the way in which the DLAT is addressed and selects the bits of the entry to be used in the translation.