Abstract: A multi-processor, multi-bus system comprises a host processor and a cluster controller coupled to a first type of bus; a local processor coupled to a second type of bus; and bus interface circuits coupled to the first and second bus types for selectively enabling the second bus to be coupled to the host processor, and for selectively enabling the first bus to be coupled to the local processor. Both bus types are asynchronous. Each bus interface circuit comprises a first-in-first-out (FIFO) register, interrupt logic, and transmitter/receiver logic. The pair of bus interface circuits together provide dual simplex data transfer between the local processor and the cluster controller which is directed by a parallel data ling (PDL) protocol. The protocol utilizes a 16-bit wide control word. The most significant bit 15, referred to as the command bit, is a "one" whenever bits 0-7 contain a command byte, while the command bit is "zero" whenever bits 0-7 contain a data byte.