Abstract: An apparatus for providing immersion cooling in a compact-format circuit card environment comprises a plurality of circuit cards, each including first and second subassemblies. Each of the subassemblies is surrounded in a longitudinal-lateral plane by a corresponding first or second perimeter frame. The first and second subassemblies have first and second operating temperatures, respectively. A first temperature tank is formed by first perimeter frames and substantially surrounds the first subassemblies. A second temperature tank is formed by second perimeter frames and substantially surrounds the second circuit card subassemblies. A first temperature cooling supply line selectively introduces the first cooling fluid into the first temperature tank for at least partially inducing the first operating temperature. A second temperature cooling supply line selectively introduces the second cooling fluid into the second temperature tank for at least partially inducing the second operating temperature.

Abstract: An apparatus for providing immersion cooling in a compact-format circuit card environment comprises a plurality of circuit cards. A plurality of thermal energy transfer devices is provided, each thermal energy transfer device at least partially inducing a respective one of first and second operating temperatures to a corresponding circuit card subassembly. At least one first temperature cooling manifold is in selective fluid communication with at least one first operating temperature thermal energy transfer device. At least one second temperature cooling manifold is in selective fluid communication with at least one second operating temperature thermal energy transfer device. A plurality of manifold interfaces is provided, each manifold interface being in fluid communication with a corresponding thermal energy transfer device. A housing includes first and second operating fluid inlets in fluid communication with first and second operating fluid outlets, respectively.

Abstract: One embodiment describes a superconducting cell array logic circuit system. The system includes a plurality of superconducting cells arranged in an array of at least one row and at least one column. The superconducting cell array logic circuit system can be configured to implement a logic operation on at least one logic input signal received at at least one respective input associated with the respective at least one row to provide at least one logic output signal on at least one respective output associated with the at least one column based on a predetermined selective coupling of the at least one input to the at least one output via the plurality of superconducting cells.