Abstract: Various systems and methods for reducing cross coupling in proximate signals are disclosed. As one example, a system for reducing cross-coupling in adjacent signals that includes an active slew rate limiter circuit is disclosed. The active slew rate limiter circuit is operable to receive an input signal, and to provide an output signal based on the input signal with a controlled slew rate. In some cases, such systems may be included within a storage device that includes a read head. In such cases, the systems may operate to assure a substantially constant power dissipation within the read head.

Abstract: Various systems and methods for reducing cross coupling in proximate signals are disclosed. As one example, a system for reducing cross-coupling in adjacent signals that includes an active slew rate limiter circuit is disclosed. The active slew rate limiter circuit is operable to receive an input signal, and to provide an output signal based on the input signal with a controlled slew rate. In some cases, such systems may be included within a storage device that includes a read head. In such cases, the systems may operate to assure a substantially constant power dissipation within the read head.

Abstract: A differential input/differential output converter circuit. The circuit comprises differential complementary input modules each comprising cross-coupled devices for biasing current mirror masters to a condition that increases the operating speed in response to a transition in the differential input signals. Certain current mirror masters are biased to a strong threshold condition and other current mirror masters are biased to a weak threshold condition responsive to a state of the differential input signals. According to another embodiment, the converter circuit further comprises a boost circuit capacitively coupled to the converter circuit for providing further speed improvements.

Abstract: A write driver circuit selectively provides a write current through a write head in first and second opposite directions. The write driver circuit is connected to the write head through an interconnect. The write driver circuit provides an incident write current signal through the interconnect to the write head, and also provides a reflection cancellation signal through the interconnect to the write head. In an exemplary embodiment, the incident write current signal is provided by providing an incident voltage signal across the write head, and the reflection cancellation signal is provided by providing a reflection cancellation voltage signal across the write head. In an exemplary embodiment, the reflection cancellation signal is a delayed and filtered version of the incident write current signal that cancels a reflected signal that is reflected at the interface between the interconnect and the write head due to impedance mismatching.

Abstract: A write driver circuit selectively provides write current through a write head in first and second opposite directions. First and second active devices are driven with first and second pre-drive signals. Third and fourth active devices are driven with third and fourth pre-drive signals. First and second pull-up resistances are provided respectively between the first and second active devices and a fixed voltage, and third and fourth pull-up resistances are provided respectively between the third and fourth active devices and the fixed voltage. A first capacitor is connected between the first active device and an intermediate point of the third pull-up resistance, and a second capacitor is connected between the second active device and an intermediate point of the fourth pull-up resistance.

Abstract: A write driver circuit selectively provides write current through a write head in first and second opposite directions. First and second active devices are driven with first and second pre-drive signals. Third and fourth active devices are driven with third and fourth pre-drive signals. First and second pull-up resistances are provided respectively between the first and second active devices and a fixed voltage, and third and fourth pull-up resistances are provided respectively between the third and fourth active devices and the fixed voltage. A first capacitor is connected between the first active device and an intermediate point of the third pull-up resistance, and a second capacitor is connected between the second active device and an intermediate point of the fourth pull-up resistance.

Abstract: A write driver circuit selectively provides a write current through a write head in first and second opposite directions. The write driver circuit is connected to the write head through an interconnect. The write driver circuit provides an incident write current signal through the interconnect to the write head, and also provides a reflection cancellation signal through the interconnect to the write head. In an exemplary embodiment, the incident write current signal is provided by providing an incident voltage signal across the write head, and the reflection cancellation signal is provided by providing a reflection cancellation voltage signal across the write head. In an exemplary embodiment, the reflection cancellation signal is a delayed and filtered version of the incident write current signal that cancels a reflected signal that is reflected at the interface between the interconnect and the write head due to impedance mismatching.