Abstract: A common reliability and serviceability (RAS) bus is connected to each functional combination of LSI apparatus, i.e., storage control, central processing unit (CPU), input/output (I/O) attachments and devices, and system control adapter constituting a computer system. The common RAS bus includes a unique address line to facilitate discrete addressing of each functional unit from the system control adapter. Logic is included in each I/O type of functional unit which is responsive to the address signal and a test mode signal for degating or blocking data normally transferring between the functional units.Other logic provides control signals for causing the addressed functional unit to go thru one clock cycle, one shift cycle, one machine cycle or one instruction cycle. This enables the addressed unit to go thru an operation after a test pattern has been loaded into the functional unit while the system continues to operate concurrently, if the addressed unit is other than the CPU.