Patents by Inventor Robert James Catherall

Robert James Catherall has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11822462
    Abstract: A method and computer program for generating code coverage information during testing of a code sequence are described, in which the code sequence comprises decisions, each having one or more conditions as inputs. The method includes executing the code sequence on target processing circuitry under the control of test stimuli and maintaining, in memory, a code coverage table for at least one decision. When a decision is evaluated, a bitstring is created within a storage element, each position in the bitstring being associated with one of the conditions and the value in that position representing the value of that condition used in evaluating the decision. The bitstring is used to identify the entry, in the code coverage table associated with the evaluated decision, for that combination of values of the conditions, and a confirmation value is recorded in that entry, indicating that the decision has been evaluated for that entry.
    Type: Grant
    Filed: July 5, 2019
    Date of Patent: November 21, 2023
    Assignee: Arm Limited
    Inventors: Sanne Wouda, Robert James Catherall
  • Patent number: 11550651
    Abstract: There is provided execution circuitry. Storage circuitry retains a stored state of the execution circuitry. Operation receiving circuitry receives, from issue circuitry, an operation signal corresponding to an operation to be performed that accesses the stored state of the execution circuitry from the storage circuitry. Functional circuitry seeks to perform the operation in response to the operation signal by accessing the stored state of the execution circuitry from the storage circuitry. Delete request receiving circuitry receives a deletion signal and in response to the deletion signal, deletes the stored state of the execution circuitry from the storage circuitry. State loss indicating circuitry responds to the operation signal when the stored state of the execution circuitry is not present and is required for the operation by indicating an error. In addition, there is provided a data processing apparatus comprising issue circuitry to issue an operation to execution circuitry.
    Type: Grant
    Filed: November 18, 2020
    Date of Patent: January 10, 2023
    Assignee: Arm Limited
    Inventors: Alasdair Grant, Robert James Catherall
  • Patent number: 11294989
    Abstract: A trusted content usage monitor for monitoring content usage is provided. A unique identifier generation unit generates a unique identifier indicative of content being rendered and a packet generator generates a trusted packet comprising the unique identifier. The trusted packet is trust signed by the trusted content usage monitor, so that it can be trusted by its recipient. The trusted content usage monitor has at least one mode of operation in which content rendering cannot be decoupled from operation of the unique identifier generation unit, so that generated packets can be trusted as truly indicative of content usage.
    Type: Grant
    Filed: August 10, 2018
    Date of Patent: April 5, 2022
    Assignee: ARM LIMITED
    Inventors: David John Butcher, Rhys David Copeland, Robert James Catherall, Jeremy Isle Johnson
  • Publication number: 20210318946
    Abstract: A method and computer program for generating code coverage information during testing of a code sequence are described, in which the code sequence comprises decisions, each having one or more conditions as inputs. The method includes executing the code sequence on target processing circuitry under the control of test stimuli and maintaining, in memory, a code coverage table for at least one decision. When a decision is evaluated, a bitstring is created within a storage element, each position in the bitstring being in associated with one of the conditions and the value in that position representing the value of that condition used in evaluating the decision. The bitstring is used to identify the entry, in the code coverage table associated with the evaluated decision, for that combination of values of the conditions, and a confirmation value is recorded in that entry, indicating that the decision has been evaluated for that entry.
    Type: Application
    Filed: July 5, 2019
    Publication date: October 14, 2021
    Inventors: Sanne WOUDA, Robert James CATHERALL
  • Publication number: 20210165705
    Abstract: There is provided execution circuitry. Storage circuitry retains a stored state of the execution circuitry. Operation receiving circuitry receives, from issue circuitry, an operation signal corresponding to an operation to be performed that accesses the stored state of the execution circuitry from the storage circuitry. Functional circuitry seeks to perform the operation in response to the operation signal by accessing the stored state of the execution circuitry from the storage circuitry. Delete request receiving circuitry receives a deletion signal and in response to the deletion signal, deletes the stored state of the execution circuitry from the storage circuitry. State loss indicating circuitry responds to the operation signal when the stored state of the execution circuitry is not present and is required for the operation by indicating an error. In addition, there is provided a data processing apparatus comprising issue circuitry to issue an operation to execution circuitry.
    Type: Application
    Filed: November 18, 2020
    Publication date: June 3, 2021
    Inventors: Alasdair GRANT, Robert James CATHERALL
  • Patent number: 10824451
    Abstract: Simulation of execution of a processing workload by a target hardware device is provided by providing workload data specifying the processing workload, passing the workload data to both a primary partial simulation and a complementary partial simulation that run in parallel and acquire input data from different levels of abstraction of the target hardware and then simulating execution of the processing workload using a primary partial simulation to generate primary partial result state data and using the complementary partial simulation to generate complementary partial result state data. The target hardware device may be a graphics processing unit and the workload data may specify the processing to be performed in a hardware independent form, such as, for example, OpenGL ES. The host system supporting the simulation may include a graphics processing unit serving to provide the complementary partial simulation due to its own execution of the workload data.
    Type: Grant
    Filed: February 11, 2015
    Date of Patent: November 3, 2020
    Assignee: ARM LIMITED
    Inventors: Robert James Catherall, Anthony Neil Berent, Rhys David Copeland, Mark Edgeworth, Jonathan Stephen Black
  • Publication number: 20180349570
    Abstract: A trusted content usage monitor for monitoring content usage is provided. A unique identifier generation unit generates a unique identifier indicative of content being rendered and a packet generator generates a trusted packet comprising the unique identifier. The trusted packet is trust signed by the trusted content usage monitor, so that it can be trusted by its recipient. The trusted content usage monitor has at least one mode of operation in which content rendering cannot be decoupled from operation of the unique identifier generation unit, so that generated packets can be trusted as truly indicative of content usage.
    Type: Application
    Filed: August 10, 2018
    Publication date: December 6, 2018
    Inventors: David John BUTCHER, Rhys David COPELAND, Robert James CATHERALL, Jeremy Isle Johnson
  • Patent number: 10102352
    Abstract: A trusted content usage monitor for monitoring content usage is provided. A unique identifier generation unit generates a unique identifier indicative of content being rendered and a packet generator generates a trusted packet comprising the unique identifier. The trusted packet is trust signed by the trusted content usage monitor, so that it can be trusted by its recipient. The trusted content usage monitor has at least one mode of operation in which content rendering cannot be decoupled from operation of the unique identifier generation unit, so that generated packets can be trusted as truly indicative of content usage.
    Type: Grant
    Filed: August 10, 2009
    Date of Patent: October 16, 2018
    Assignee: ARM LIMITED
    Inventors: David John Butcher, Rhys David Copeland, Robert James Catherall, Jeremy Isle Johnson
  • Publication number: 20150261551
    Abstract: Simulation of execution of a processing workload by a target hardware device is provided by providing workload data specifying the processing workload, passing the workload data to both a primary partial simulation and a complementary partial simulation that run in parallel and acquire input data from different levels of abstraction of the target hardware and then simulating execution of the processing workload using a primary partial simulation to generate primary partial result state data and using the complementary partial simulation to generate complementary partial result state data. The target hardware device may be a graphics processing unit and the workload data may specify the processing to be performed in a hardware independent form, such as, for example, OpenGL ES. The host system supporting the simulation may include a graphics processing unit serving to provide the complementary partial simulation due to its own execution of the workload data.
    Type: Application
    Filed: February 11, 2015
    Publication date: September 17, 2015
    Inventors: Robert James CATHERALL, Anthony Neil BERENT, Rhys David COPELAND, Mark EDGEWORTH, Jonathan Stephen BLACK
  • Patent number: 8159491
    Abstract: A data processing apparatus and method are provided for tracing activities of a shader program executed on shader circuitry of a data processing apparatus. The data processing apparatus comprises shader circuitry which is responsive to input data for a pixel to execute a shader program to generate a color value for the pixel. The shader program has multiple execution paths via which the color value may be generated, and which execution path is taken is dependent on the input data. An image buffer having a plurality of storage locations is provided, with each storage location being used to store the color value generated by the shader circuitry for an associated pixel. In a trace mode of operation, execution of the shader program by the shader circuitry causes a trace vector to be generated containing a plurality of items of execution path information indicative of the execution path taken, the trace vector comprising a plurality of fields, each field being used to store one item of execution path information.
    Type: Grant
    Filed: December 3, 2009
    Date of Patent: April 17, 2012
    Assignee: ARM Limited
    Inventors: Martyn Capewell, David John Butcher, Robert James Catherall, Peter James Horsman
  • Publication number: 20110035589
    Abstract: A trusted content usage monitor for monitoring content usage is provided. A unique identifier generation unit generates a unique identifier indicative of content being rendered and a packet generator generates a trusted packet comprising the unique identifier. The trusted packet is trust signed by the trusted content usage monitor, so that it can be trusted by its recipient. The trusted content usage monitor has at least one mode of operation in which content rendering cannot be decoupled from operation of the unique identifier generation unit, so that generated packets can be trusted as truly indicative of content usage.
    Type: Application
    Filed: August 10, 2009
    Publication date: February 10, 2011
    Applicant: ARM Limited
    Inventors: David John Butcher, Rhys David Copeland, Robert James Catherall, Jeremy Isle Johnson
  • Publication number: 20100149185
    Abstract: A data processing apparatus and method are provided for tracing activities of a shader program executed on shader circuitry of a data processing apparatus. The data processing apparatus comprises shader circuitry which is responsive to input data for a pixel to execute a shader program to generate a colour value for the pixel. The shader program has multiple execution paths via which the colour value may be generated, and which execution path is taken is dependent on the input data. An image buffer having a plurality of storage locations is provided, with each storage location being used to store the colour value generated by the shader circuitry for an associated pixel.
    Type: Application
    Filed: December 3, 2009
    Publication date: June 17, 2010
    Applicant: ARM LIMITED
    Inventors: Martyn Capewell, David John Butcher, Robert James Catherall, Peter James Horsman