Abstract: An integrated circuit (IC) chip containing a Delta-Sigma (??) filter module for a ?? analog-to-digital converter and a method of providing analog to digital conversion are disclosed. The IC chip includes a ?? filter that is connected to receive a digital data stream created by a ?? modulator, provide a multibit data value when a counter reaches a selected number of received bits, and reset the counter responsive to receiving a synchronization pulse. The IC chip also includes a FIFO buffer connected to store the multibit data value only when a synchronization flag is on and to send an interrupt towards a processing unit only after storing a selected number of multibit data values. The IC chip further includes a synchronization module connected to turn on the synchronization flag responsive to receiving the synchronization pulse and to turn off the synchronization flag responsive to the sending of the interrupt.

Abstract: An integrated circuit (IC) chip containing a Delta-Sigma (??) filter module for a ?? analog-to-digital converter and a method of providing analog to digital conversion are disclosed. The IC chip includes a ?? filter that is connected to receive a digital data stream created by a ?? modulator, provide a multibit data value when a counter reaches a selected number of received bits, and reset the counter responsive to receiving a synchronization pulse. The IC chip also includes a FIFO buffer connected to store the multibit data value only when a synchronization flag is on and to send an interrupt towards a processing unit only after storing a selected number of multibit data values. The IC chip further includes a synchronization module connected to turn on the synchronization flag responsive to receiving the synchronization pulse and to turn off the synchronization flag responsive to the sending of the interrupt.

Abstract: A method and circuit in which the drive strength of a FinFET transistor can be selectively modified, and in particular can be selectively reduced, by omitting the LDD extension formation in the source and/or in the drain of the FinFET. One application of this approach is to enable differentiation of the drive strengths of transistors in an integrated circuit by applying the technique to some, but not all, of the transistors in the integrated circuit. In particular in a SRAM cell formed from FinFET transistors the application of the technique to the pass-gate transistors, which leads to a reduction of the drive strength of the pass-gate transistors relative to the drive strength of the pull-up and pull-down transistors, results in improved SRAM cell performance.

Abstract: A device and method of fabricating the same are disclosed. In an example, a device includes a first fin Field Effect Transistors (finFET) formed on a substrate. The first finFET including a fin formed on the substrate. The device further includes a second finFET formed on the substrate. The first finFET and the second finFET share the fin and wherein the first finFET is without any low density doped (LDD) extension region in the substrate and wherein the second FinFET is associated with a first LDD extension region formed in the substrate such that a drive strength of the second finFET is greater relative to a drive strength of the first finFET.

Abstract: A method and circuit in which the drive strength of a FinFET transistor can be selectively modified, and in particular can be selectively reduced, by omitting the LDD extension formation in the source and/or in the drain of the FinFET. One application of this approach is to enable differentiation of the drive strengths of transistors in an integrated circuit by applying the technique to some, but not all, of the transistors in the integrated circuit. In particular in a SRAM cell formed from FinFET transistors the application of the technique to the pass-gate transistors, which leads to a reduction of the drive strength of the pass-gate transistors relative to the drive strength of the pull-up and pull-down transistors, results in improved SRAM cell performance.

Abstract: Methods, circuits and systems are provided for testing random-access memory (RAM) devices. In one embodiment, one or more test vectors are written to a RAM device. Bit-signals are read from the RAM device one line at a time and are segregated into respective sub-pluralities. Each sub-plurality is tested to determine if there is logical value equality among all of the respective bit-signals. Test signals corresponding to each of the sub-plurality determinations are provided. The test signals are collectively evaluated and an overall equality or non-equality signal is derived.

Abstract: A circuit takes a reference strobe signal as a first input, and a strobe ready signal generated from a memory that is strobed by the reference strobe signal as a second input. The circuit generates a self-timed strobe signal along with other control signals that are used to perform a subsequent memory access in a single clock cycle, thereby doubling memory access bandwidth.

Abstract: A circuit takes a reference strobe signal as a first input, and a strobe ready signal generated from a memory that is strobed by the reference strobe signal as a second input. The circuit generates a self-timed strobe signal along with other control signals that are used to perform a subsequent memory access in a single clock cycle, thereby doubling memory access bandwidth.