Abstract: An integrated circuit (IC) chip containing a Delta-Sigma (??) filter module for a ?? analog-to-digital converter and a method of providing analog to digital conversion are disclosed. The IC chip includes a ?? filter that is connected to receive a digital data stream created by a ?? modulator, provide a multibit data value when a counter reaches a selected number of received bits, and reset the counter responsive to receiving a synchronization pulse. The IC chip also includes a FIFO buffer connected to store the multibit data value only when a synchronization flag is on and to send an interrupt towards a processing unit only after storing a selected number of multibit data values. The IC chip further includes a synchronization module connected to turn on the synchronization flag responsive to receiving the synchronization pulse and to turn off the synchronization flag responsive to the sending of the interrupt.

Abstract: An integrated circuit (IC) chip containing a Delta-Sigma (??) filter module for a ?? analog-to-digital converter and a method of providing analog to digital conversion are disclosed. The IC chip includes a ?? filter that is connected to receive a digital data stream created by a ?? modulator, provide a multibit data value when a counter reaches a selected number of received bits, and reset the counter responsive to receiving a synchronization pulse. The IC chip also includes a FIFO buffer connected to store the multibit data value only when a synchronization flag is on and to send an interrupt towards a processing unit only after storing a selected number of multibit data values. The IC chip further includes a synchronization module connected to turn on the synchronization flag responsive to receiving the synchronization pulse and to turn off the synchronization flag responsive to the sending of the interrupt.

Abstract: Methods, circuits and systems are provided for testing random-access memory (RAM) devices. In one embodiment, one or more test vectors are written to a RAM device. Bit-signals are read from the RAM device one line at a time and are segregated into respective sub-pluralities. Each sub-plurality is tested to determine if there is logical value equality among all of the respective bit-signals. Test signals corresponding to each of the sub-plurality determinations are provided. The test signals are collectively evaluated and an overall equality or non-equality signal is derived.

Abstract: A circuit takes a reference strobe signal as a first input, and a strobe ready signal generated from a memory that is strobed by the reference strobe signal as a second input. The circuit generates a self-timed strobe signal along with other control signals that are used to perform a subsequent memory access in a single clock cycle, thereby doubling memory access bandwidth.

Abstract: A circuit takes a reference strobe signal as a first input, and a strobe ready signal generated from a memory that is strobed by the reference strobe signal as a second input. The circuit generates a self-timed strobe signal along with other control signals that are used to perform a subsequent memory access in a single clock cycle, thereby doubling memory access bandwidth.