Abstract: A flip-flop is disclosed. The flip-flop includes a first latch for receiving at least one bit and a second latch coupled to the first latch for storing the at least one bit from the first latch. The size of the second latch is minimized to reduce power consumption. The flip-flop also includes a multiplexor coupled to the first latch and to the second latch for outputting the at least one bit from the first latch, when a clock to the multiplexor is active and for outputting the at least one bit from the second latch when the clock is inactive. A system and method in accordance with the present invention optimize power consumption in a flip-flop through the use of a multiplexor for the output function. As a result, the size of the slave latch can be minimized, which reduces the overall power consumption of the device.

Abstract: A flip-flop is disclosed. The flip-flop includes a first latch for receiving at least one bit and a second latch coupled to the first latch for storing the at least one bit from the first latch. The size of the second latch is minimized to reduce power consumption. The flip-flop also includes a multiplexor coupled to the first latch and to the second latch for outputting the at least one bit from the first latch, when a clock to the multiplexor is active and for outputting the at least one bit from the second latch when the clock is inactive. A system and method in accordance with the present invention optimize power consumption in a flip-flop through the use of a multiplexor for the output function. As a result, the size of the slave latch can be minimized, which reduces the overall power consumption of the device.

Abstract: A system and method of controlling the operation of a storage device (a semiconductor latch in its preferred embodiment) to reduce the power consumed by the storage device. The system uses a split clock signal to control the operation of the latch, with an early enable signal and a late enable signal being operable to turn the latch on when needed and to turn it off when it is not needed. More particularly, the present invention logically generates clocking control signals for the latch using the early enable signal and the late enable signal to control the operation of the latch and to reduce power consumption and allow for an increased period of time to make a decision whether to turn off the early enable signal.