Abstract: A method of making an inverter comprising: a substrate; a first transistor in thermal contact with the substrate, wherein the transistor comprises a gate; the substrate sintered to a heat sink through a sintered layer; an encapsulant that at least partially encapsulates the first transistor; and a Kelvin connection to the transistor gate.

Abstract: A transistor package comprising: a substrate; a first transistor in thermal contact with the substrate, wherein the transistor comprises a gate; the substrate sintered to a heat sink through a sintered layer; an encapsulant that at least partially encapsulates the first transistor; and a Kelvin connection to the transistor gate.

Abstract: A transistor package comprising: a substrate; a first transistor in thermal contact with the substrate, wherein the transistor comprises a gate; the substrate sintered to a heat sink through a sintered layer; an encapsulant that at least partially encapsulates the first transistor; and a Kelvin connection to the transistor gate.

Abstract: A semiconductor device includes: a housing; a substrate inside the housing; first and second semiconductor circuits on the substrate; and first and second planar terminals electrically connected to the first and second semiconductor circuits, respectively, the first and second planar terminals stacked on top of each other, wherein each of the first and second planar terminals extends away from the housing.

Abstract: A transistor package comprising: a substrate; a first transistor in thermal contact with the substrate, wherein the transistor comprises a gate; the substrate sintered to a heat sink through a sintered layer; an encapsulant that at least partially encapsulates the first transistor; and a Kelvin connection to the transistor gate.

Abstract: A semiconductor device includes: a housing; a substrate inside the housing; first and second semiconductor circuits on the substrate; and first and second planar terminals electrically connected to the first and second semiconductor circuits, respectively, the first and second planar terminals stacked on top of each other, wherein each of the first and second planar terminals extends away from the housing.

Abstract: A transistor package comprising: a substrate; a first transistor in thermal contact with the substrate, wherein the transistor comprises a gate; the substrate sintered to a heat sink through a sintered layer; an encapsulant that at least partially encapsulates the first transistor; and a Kelvin connection to the transistor gate.

Abstract: A method of fabricating a stator for an electric motor is provided. The method includes providing a plurality of stator laminations. Each stator lamination of the plurality of stator laminations is a copy of the same stator lamination pattern. The method further includes stacking the plurality of stator laminations in a sequence along an axis, comprising periodically varying rotational orientations of the stator laminations in the sequence. The method further includes joining the plurality of stator laminations as stacked in the sequence.

Abstract: The various implementations described herein include inverter devices and systems. In one aspect, an inverter includes: a case; a capacitor within the case having a first terminal and a second terminal; a first bus bar including a first portion within the case and a second portion extending from the case to contact a first transistor; a second bus bar including a first portion situated in the case and a second portion extending from the case to contact a second transistor; and a phase-out bus bar including a first portion situated in the case, a second portion extending from the case to contact the first transistor, and a third portion extending from the case to contact the second transistor.

Abstract: A drive unit for an electric vehicle includes a stator having an axis extending through an opening in the middle of the stator, a case, a clamp to fasten the stator within the case and a fastener. The case includes a boss with an opening having an axis and a ramp adjacent to the boss and slanting toward the axis of the stator as it extends away from the opening of the boss. The clamp includes a first portion to contact a side of the stator to provide a radial force to the stator and a second portion to contact an end of the stator to provide an axial force to the stator. The fastener is inserted through the clamp into the boss. The slanted edge is configured to slide against the ramp when the fastener is inserted into the boss, to generate the radial force.

Abstract: A method of fabricating a stator for an electric motor is provided. The method includes providing a plurality of stator laminations. Each stator lamination of the plurality of stator laminations is a copy of the same stator lamination pattern. The method further includes stacking the plurality of stator laminations in a sequence along an axis, comprising periodically varying rotational orientations of the stator laminations in the sequence. The method further includes joining the plurality of stator laminations as stacked in the sequence.

Abstract: The various implementations described herein include inverter devices and systems. In one aspect, an inverter includes: a case; a capacitor within the case having a first terminal and a second terminal; a first bus bar including a first portion within the case and a second portion extending from the case to contact a first transistor; a second bus bar including a first portion situated in the case and a second portion extending from the case to contact a second transistor; and a phase-out bus bar including a first portion situated in the case, a second portion extending from the case to contact the first transistor, and a third portion extending from the case to contact the second transistor.

Abstract: A semiconductor device includes housing, a substrate, a first semiconductor die, a second semiconductor die, a first terminal, and a second terminal. The first terminal in a first terminal plane couples to the first semiconductor die. The second terminal has a contact portion in a contact portion plane within the housing that couples to the second semiconductor die, a main portion in a main portion plane partially within the housing, the main portion plane substantially parallel to and offset from the first terminal plane, and the main portion plane substantially parallel to and offset from the contact portion plane, and an offsetting portion within the housing and that connects the contact portion to the main portion. At least some of the main portion of the second terminal overlaps the first terminal and the first terminal and the main portion of the second terminal extend from the housing in a same direction.

Abstract: A packaged semiconductor device has a plurality of leads. A respective lead is to be welded to an electrical coupling that has a substantially rectangular end section. The end section has a width that is greater than a width of the respective lead. The respective lead is aligned within the width of the end section, such that the respective lead extends in a direction substantially perpendicular to the width of the end section. With the respective lead and the end section aligned, the respective lead is welded to the end section.

Abstract: The various implementations described herein include inverter devices and systems. In one aspect, an inverter includes: a case; a capacitor within the case having a first terminal and a second terminal; a first bus bar including a first portion within the case and a second portion extending from the case to contact a first transistor; a second bus bar including a first portion situated in the case and a second portion extending from the case to contact a second transistor; and a phase-out bus bar including a first portion situated in the case, a second portion extending from the case to contact the first transistor, and a third portion extending from the case to contact the second transistor.

Abstract: The various implementations described herein include inverter devices and systems. In one aspect, an inverter includes: a case; a capacitor within the case having a first terminal and a second terminal; a first bus bar including a first portion within the case and a second portion extending from the case to contact a first transistor; a second bus bar including a first portion situated in the case and a second portion extending from the case to contact a second transistor; and a phase-out bus bar including a first portion situated in the case, a second portion extending from the case to contact the first transistor, and a third portion extending from the case to contact the second transistor.

Abstract: A packaged semiconductor device has a plurality of leads. A respective lead is to be welded to an electrical coupling that has a substantially rectangular end section. The end section has a width that is greater than a width of the respective lead. The respective lead is aligned within the width of the end section, such that the respective lead extends in a direction substantially perpendicular to the width of the end section. With the respective lead and the end section aligned, the respective lead is welded to the end section.

Abstract: The various implementations described herein include inverter devices and systems. In one aspect, an inverter includes: a case; a capacitor within the case having a first terminal and a second terminal; a first bus bar including a first portion within the case and a second portion extending from the case to contact a first transistor; a second bus bar including a first portion situated in the case and a second portion extending from the case to contact a second transistor; and a phase-out bus bar including a first portion situated in the case, a second portion extending from the case to contact the first transistor, and a third portion extending from the case to contact the second transistor.

Abstract: The various implementations described herein include inverter devices and systems. In one aspect, an inverter includes: a case; a capacitor within the case having a first terminal and a second terminal; a first bus bar including a first portion within the case and a second portion extending from the case to contact a first transistor; a second bus bar including a first portion situated in the case and a second portion extending from the case to contact a second transistor; and a phase-out bus bar including a first portion situated in the case, a second portion extending from the case to contact the first transistor, and a third portion extending from the case to contact the second transistor.

Abstract: A busbar locating component includes: one or more first attachments configured for attaching a busbar layer to the busbar locating component; one or more bays each configured to contain and position an assembly of transistors essentially perpendicular to the busbar layer for connection; and a plurality of slots, each slot configured to contain and position a busbar relative to the busbar layer for connection.