Patents by Inventor Robert James Todd

Robert James Todd has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230375784
    Abstract: An optical processing system comprises a first integrated optical waveguide array; a first bundle of optical fibres; the optical fibres being coupled to the first integrated optical waveguide array by a first coupler; the optical fibres being further coupled to an optical Fourier stage; a second bundle of optical fibres being coupled to the optical Fourier stage; a second integrated optical waveguide array; and a second coupler for coupling the second bundle of optical fibres to the second integrated optical waveguide array.
    Type: Application
    Filed: September 6, 2021
    Publication date: November 23, 2023
    Inventor: Robert James TODD
  • Patent number: 11094817
    Abstract: A semiconductor device includes a local oxidation of silicon (LOCOS) structure and a shallow trench isolation (STI) structure formed over a semiconductor substrate. A source region is located between the LOCOS structure and the STI structure. A gate structure is located between the source region and the LOCOS structure. A contact may be located over the STI structure electrically connect to the gate structure.
    Type: Grant
    Filed: January 23, 2020
    Date of Patent: August 17, 2021
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Xiaoju Wu, Robert James Todd, Henry Litzmann Edwards
  • Patent number: 11062101
    Abstract: A method to incorporate multiple independent optical correlators into one system. By “independent optical correlator,” we mean an optical correlator comprising of an input SLM, filter SLM, and camera, combined with appropriate coherent illumination and Fourier transforming lenses. By “one system” we mean a single optical system which utilises the elements of each of the independent correlators multiple times.
    Type: Grant
    Filed: April 16, 2018
    Date of Patent: July 13, 2021
    Assignee: Optalysys Limited
    Inventors: Nicholas James New, Robert James Todd
  • Publication number: 20200161471
    Abstract: A semiconductor device includes a local oxidation of silicon (LOCOS) structure and a shallow trench isolation (STI) structure formed over a semiconductor substrate. A source region is located between the LOCOS structure and the STI structure. A gate structure is located between the source region and the LOCOS structure. A contact may be located over the STI structure electrically connect to the gate structure.
    Type: Application
    Filed: January 23, 2020
    Publication date: May 21, 2020
    Inventors: Xiaoju Wu, Robert James Todd, Henry Litzmann Edwards
  • Publication number: 20200097691
    Abstract: A method to incorporate multiple independent optical correlators into one system. By “independent optical correlator,” we mean an optical correlator comprising of an input SLM, filter SLM, and camera, combined with appropriate coherent illumination and Fourier transforming lenses. By “one system” we mean a single optical system which utilises the elements of each of the independent correlators multiple times.
    Type: Application
    Filed: April 16, 2018
    Publication date: March 26, 2020
    Inventors: Nicholas James NEW, Robert James TODD
  • Patent number: 10580890
    Abstract: A semiconductor device includes a NMOS transistor with a back gate connection and a source region disposed on opposite sides of the back gate connection. The source region and back gate connection are laterally isolated by an STI oxide layer which surrounds the back gate connection. The NMOS transistor has a gate having a closed loop configuration, extending partway over a LOCOS oxide layer which surrounds, and is laterally separated from, the STI oxide layer. A lightly-doped drain layer is disposed on opposite sides of the NMOS transistor, extending under the LOCOS oxide layer to a body region of the NMOS transistor. The LOCOS oxide layer is thinner than the STI oxide layer, so that the portion of the gate over the LOCOS oxide layer provides a field plate functionality. The NMOS transistor may optionally be surrounded by an isolation structure which extends under the NMOS transistor.
    Type: Grant
    Filed: December 4, 2017
    Date of Patent: March 3, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Xiaoju Wu, Robert James Todd, Henry Litzmann Edwards
  • Publication number: 20190172946
    Abstract: A semiconductor device includes a NMOS transistor with a back gate connection and a source region disposed on opposite sides of the back gate connection. The source region and back gate connection are laterally isolated by an STI oxide layer which surrounds the back gate connection. The NMOS transistor has a gate having a closed loop configuration, extending partway over a LOCOS oxide layer which surrounds, and is laterally separated from, the STI oxide layer. A lightly-doped drain layer is disposed on opposite sides of the NMOS transistor, extending under the LOCOS oxide layer to a body region of the NMOS transistor. The LOCOS oxide layer is thinner than the STI oxide layer, so that the portion of the gate over the LOCOS oxide layer provides a field plate functionality. The NMOS transistor may optionally be surrounded by an isolation structure which extends under the NMOS transistor.
    Type: Application
    Filed: December 4, 2017
    Publication date: June 6, 2019
    Applicant: Texas Instruments Incorporated
    Inventors: Xiaoju Wu, Robert James Todd, Henry Litzmann Edwards