Abstract: Embodiments of the invention are directed to a computer-implemented method of performing routing operations for an integrated circuit (IC) design. The computer-implemented method includes identifying, using a processor system, a location of a buffer bay in the IC design. One or more blockage areas associated with the buffer bay are identified. A pattern of the one or more blockage areas is determined, and the pattern includes one or more blockage area exit locations. A component is placed within the buffer bay. Based at least in part on information of the pattern, a routing path is determined from the component through the pattern to one of the one or more blockage area exit locations.

Abstract: Aspects of the invention include parallel creation of via meshes in an integrated circuit. Aspects include obtaining a plurality of via mesh creation jobs for an integrated circuit, obtaining existing wires and design rules for the integrated circuit, and partitioning the plurality of via mesh creation jobs into a plurality of sets of jobs, wherein the jobs in each set have a proximity to at least one another job in the set that is less than a threshold distance. Aspects also include assigning each of the plurality of sets of jobs to different processing units and creating, by each of the different processing units, a via mesh for each of the jobs in the assigned set of jobs.

Abstract: This is an approach for data-driven cutout to support mixed transistor-level timing analysis and abstract timing analysis. The approach may include specifying a plurality of rules to parameterize a small kernel pattern. Further, the approach may include specifying one or more post-matching rules for joining the small kernel pattern matches into a full-size cutout match. The approach may include generating a plurality of timing rules for each of a specific type of a kernel. The approach may also include, identifying one or more repetitive structures and/or symmetries within the small kernel pattern match. Further yet, the approach may include stitching the small kernel matches and composing the stitched small kernel matches with a correct pin correlation to a cutout. Also, the approach may include determining the kernel timing for the composed stitched kernel matches, based on the generated timing rules.

Abstract: Embodiments of the present disclosure provide methods, systems, and computer program products for implementing intelligent timing aware metal fill optimization for an IC layout. The disclosed methods enable fill tooling to identify the existing metal tile density and provide timing-aware metal fill insertion to specifically target density requirements and enable effective timing characteristics of signal path nets.

Abstract: Embodiments of the present disclosure provide methods, systems, and computer program products for implementing retargeting-aware metal fill optimization for an IC layout. A disclosed embodiment enables a metal fill optimization design tool to identify empty space adjacent to the active metal shapes of one or more signal path nets in a metal shapes infrastructure and provide retargeting-aware metal fill insertion into empty space configured to specifically avoid foundry retargeting operations having adverse impacts on timing characteristics of signal path nets.

Abstract: Embodiments include translation of an integrated circuit design data into a production file. Aspects of the invention include identifying a top cell in the integrated circuit design data and a first cell-file associated with the top cell, assigning the first cell-file to a first translation module of a plurality of translation modules, and receiving, from the first translation module, an identification of child cells referenced by the first cell-file. Aspects also include assigning cell-files of the integrated circuit design data that correspond to each of the child cells to different translation modules of the plurality of translation modules, receiving, by a merger module, a single-cell production file from each of the plurality of translation modules, wherein each single-cell production file corresponds to a cell in the integrated circuit design data, and combining, by the merger module, the single-cell production files to create the production file.

Abstract: Timing constraint auto-creation for integrated circuit testing includes analyzing an integrated circuit design using a first clocking attribute, wherein the first clocking attribute describes a first clock for the integrated circuit design; identifying, based on the analysis and the first clocking attribute, design features of the integrated circuit design necessitating timing constraints; and generating, based on the identified design features, the timing constraints for the static timing analysis of the integrated circuit design.

Abstract: Density-aware fill with boundary compensation is disclosed, including identifying, based on one or more metal density constraints, a minimum density requirement for an integrated circuit (IC) design; determining a metal density for a tile of the IC design; identifying a target amount of metal fill based on metal density and the minimum density requirement; and integrating metal fill in the IC design based on the target amount of metal fill.

Abstract: The present disclosure describes systems and methods for performing timing analysis of circuit designs. According to an embodiment, a method includes assigning a timing margin to a non-scan latch of a circuit design and performing a timing analysis on the circuit design using the timing margin for the non-scan latch to produce timing results for the circuit design. The timing results include a slack value. The method also includes calculating a credit based on the slack value and updating the slack value based on the credit.

Abstract: An extendible ramp for entrance to or egress from vehicles, such as buses, includes sensors arranged to detect whether the ramp abuts an obstruction. The ramp assembly comprises a chassis, a ramp extendible from the chassis, a frame which carries the chassis and a sensor arranged to sense movement of the chassis relative to the frame. The chassis is mounted in the frame such that it moves relative to the frame in response to both abutment of the leading edge of the ramp against an obstacle and in response to vertical force applied to the top of the extended, or partially extended ramp. The chassis also moves relative to the frame in response to a force applied to the side of the extended or partially extended ramp.

Abstract: A method for hierarchical very large scale integration design comprises representing a structure of the hierarchical very large scale integrated design as a graph comprising design objects. The method further comprises specifying a transformation behavior applied to the design objects, and processing, top-down, the graph to perform the transformation on the hierarchical very large scale integrated design.

Abstract: There is provided screen apparatus comprising side walls having a lower edge portion configured to accept tubular screen support members. An upper edge extends from the inlet end of the side walls to an apex from which a declining edge extends to the foot of the side walls. The lower edge, upper edge and declining edge are each provided with edge stiffening. A torque tube is secured between the respective exciter mount castings, the torque tube and stiffened side wall being selected to provide that the first fundamental frequency mode greater than the exciter frequency is at least 2 Hz greater than the exciter frequency and the first fundamental frequency below the exciter frequency is at least 2 Hz lower than the exciter frequency.

Abstract: An extendable ramp assembly includes a chassis, a first ramp slidably movable relative to the chassis and hingably connected to the chassis, and a second ramp carried by the first ramp and movable relative to the chassis and the first ramp. Separate structure is provided for extending and retracting both the first and second ramps. A first mechanism is provided for detecting whether either or both of the first and second ramps abuts an obstruction when at least one of the ramps is being extended. A second mechanism is provided for stopping the extension of at least one of the ramps or for retracting at least one of the ramps in the event of the detecting mechanism detecting the obstruction.

Abstract: There is provided screen apparatus comprising side walls having a lower edge portion configured to accept tubular screen support members. An upper edge extends from the inlet end of the side walls to an apex from which a declining edge extends to the foot of the side walls. The lower edge, upper edge and declining edge are each provided with edge stiffening. A torque tube is secured between the respective exciter mount castings, the torque tube and stiffened side wall being selected to provide that the first fundamental frequency mode greater than the exciter frequency is at least 2 Hz greater than the exciter frequency and the first fundamental frequency below the exciter frequency is at least 2 Hz lower than the exciter frequency.