Abstract: Security measures for signal paths with tree structures can be implemented at design phase using an EDA software program or tool with security feature functionality that, when executed by a computing system, directs the computing system to: display a canvas through which components of a circuit are arranged; and provide a menu of commands, including an option to add components from a library to the canvas and an option to secure a tree. In response to receiving a selection of the option to secure the tree, the system can be directed to add a hardware countermeasure coupled to at least two lines or terminal nodes of a tree structure identified from components on the canvas or in a netlist corresponding to a circuit's design.

Abstract: Security measures for signal paths with tree structures can be implemented at design phase using an EDA software program or tool with security feature functionality that, when executed by a computing system, directs the computing system to: display a canvas through which components of a circuit are arranged; and provide a menu of commands, including an option to add components from a library to the canvas and an option to secure a tree. In response to receiving a selection of the option to secure the tree, the system can be directed to add a hardware countermeasure coupled to at least two lines or terminal nodes of a tree structure identified from components on the canvas or in a netlist corresponding to a circuit's design.

Abstract: An integrated circuit comprises a power input, digital logic circuitry, a plurality of charge stores, and obscuring circuitry. The charge stores are configured to receive power from the power input, are distributed through the digital logic circuitry and are capable of providing power to the digital logic circuitry. The obscuring circuitry is configured to obscure electromagnetic emissions associated with flow of current in current loops between the plurality of charge stores and the digital logic circuitry by switching between a plurality of different charge store activation patterns, wherein each charge store activation pattern describes a different selection of one or more of the plurality of charge stores providing power to the digital logic circuitry at a given time.

Abstract: Security measures for signal paths with tree structures can be implemented at design phase using an EDA software program or tool with security feature functionality that, when executed by a computing system, directs the computing system to: display a canvas through which components of a circuit are arranged; and provide a menu of commands, including an option to add components from a library to the canvas and an option to secure a tree. In response to receiving a selection of the option to secure the tree, the system can be directed to add a hardware countermeasure coupled to at least two lines or terminal nodes of a tree structure identified from components on the canvas or in a netlist corresponding to a circuit's design.

Abstract: An apparatus is provided to enable power supply input to be isolated from power supply output. Power is received from a first power signal at a first of a plurality of charge stores. A second power signal is output from a second of the plurality of charge stores. The second power signal is isolated from the first power supply. The first charge store can be charged from the power input whilst isolated from the power output. The second charge store can be discharged to the power output, while isolated from the power input.

Abstract: An apparatus includes a power input, a power output, and a plurality of independent powering units each comprising at least one charge store. Each of the plurality of powering units is capable of receiving power from the power input while isolating the power output, and each of the plurality of powering units is capable of outputting power to the power output while isolating the power input.

Abstract: A data processing apparatus 2 includes processing circuitry 4 performing processing operations which move the processing circuitry 4 between logical states. Monitoring circuitry 18 monitors logical state variables of the processing circuitry and these are supplied to prediction circuitry 30 which detects predetermined patterns within the logical states which are indicative (previously correlated with) of a future potential temporary insufficiency in the supply power to the processing circuitry 4. When such a pattern is detected, then power control circuitry 8,10 serves to trigger a mitigation response to counteract the future potential temporary insufficiency in power supply, such as temporarily reducing the clock frequency and/or boosting the supply voltage.

Abstract: Power is received from a first power signal a first of a plurality of charge stores. A second power signal is output from a second of the plurality of charge stores. The second power signal is isolated from the first power supply.

Abstract: Power is received from a first power signal at a first of a plurality of charge stores. A second power signal is output from a second of the plurality of charge stores. The second power signal is isolated from the first power supply.

Abstract: A computer-implemented method of integrated circuit design comprises: using a computer, producing an integrated circuit layout for multiple instances of a circuitry element, wherein interface components in one instance of said circuitry element communicate with complementary interface components in an adjacent instance of said circuitry element, said interface components being identical between said multiple instances; said producing step comprising: for one instance of said circuitry element, generating an integrated circuit layout for said one instance of said circuitry element on the basis of timing parameters of said complementary interface components with which said one instance communicates in use; detecting timing characteristics of said interface components of said one instance of said circuitry element; applying said detected timing characteristics as said timing parameters of said complementary interface components; and repeating said generating step.

Abstract: A data processing apparatus 2 includes processing circuitry 4 performing processing operations which move the processing circuitry 4 between logical states. Monitoring circuitry 18 monitors logical state variables of the processing circuitry and these are supplied to prediction circuitry 30 which detects predetermined patterns within the logical states which are indicative (previously correlated with) of a future potential temporary insufficiency in the supply power to the processing circuitry 4. When such a pattern is detected, then power control circuitry 8,10 serves to trigger a mitigation response to counteract the future potential temporary insufficiency in power supply, such as temporarily reducing the clock frequency and/or boosting the supply voltage.

Abstract: A computer-implemented method of integrated circuit design comprises: using a computer, producing an integrated circuit layout for multiple instances of a circuitry element, wherein interface components in one instance of said circuitry element communicate with complementary interface components in an adjacent instance of said circuitry element, said interface components being identical between said multiple instances; said producing step comprising: for one instance of said circuitry element, generating an integrated circuit layout for said one instance of said circuitry element on the basis of timing parameters of said complementary interface components with which said one instance communicates in use; detecting timing characteristics of said interface components of said one instance of said circuitry element; applying said detected timing characteristics as said timing parameters of said complementary interface components; and repeating said generating step.

Abstract: An aerofoil comprises a leading edge and a trailing edge which define a mean chord length, and the aerofoil having an inner or root end adapted for attachment to an aircraft, and an outer end which includes a tip which is adapted in use to divide the airflow into two generally equal vortices one being an inner vortex and the other being an outer vortex the inner vortex being arranged to trail from an outer edge of a forward region of the tip and pass over a rear region of the tip.

Abstract: A propeller (10a) comprising a plurality of propeller blades (9a) each having a root end (11a) attached to the central propeller disc or hub (12a), an intermediate portion (13a) extending from the root end (11a) and having a generally aerofoil cross section extending chordwise between a leading edge (14a) and a trailing edge (15a), and the blade (9a) having a tip (19) at an end of the intermediate portion (13a) remote from the root end (11a), the tip (19) having a leading edge portion (20) extending forwardly from a junction (21) with the leading edge (14a) of the intermediate portion (13a) thus to provide a discontinuity or notch (25) in the leading edge (14a) of the blade (9a) at the junction (21).