Abstract: A trinary input circit for an MOSFET integrated circuit includes a biasing stage formed by using a standard inverter, whose output is connected to its input so as to establish a particular bias voltage level when the input to the trinary input circuit is left floating. The output of the biasing stage is applied to the inputs of a second inverter stage having a higher beta ratio than the bias stage and to the input of a third inverter stage having a lower beta ratio. The bias stage when left open circuited will seek a quiescent voltage which is above the switching threshold of the second stage and below the switching threshold of the third stage. Thus, as a result of the relative beta ratios of the three stages when the input to the bias stage is left open, the bias stage will seek a particular voltage level such that the high beta ratio stage produces a logic 0 output and the low beta ratio stage produces a logic 1 output.

Abstract: Method and circuit for both outputting and inputting data by way of a single pin connector for an integrated circuit chip is disclosed. Data from the chip is fed through an output buffer on the chip and a standard pin connector to external circuitry. The input and the output of the output buffer are connected to separate logic inputs of a comparator such as an EXCLUSIVE OR gate. For data output, the external circuitry allows the output buffer to follow the input of the buffer, in which case the output of the EXCLUSIVE OR gate is a logic 0. However, when the external circuitry overrides the output of the output buffer causing the output to be different from the input to the buffer, the output of the EXCLUSIVE OR gate produces a logic 1 signal which indicates that data is being input and that the data at the pin connector is valid input data.