Abstract: A hermetically sealed electronic device and method of fabrication are provided. A base layer of a wafer is created using a substrate formed from ultra-thin glass or ceramic using panel or roll to roll processing. One or more layers are bonded to the base layer. The wafer is singulated into a plurality of electronic devices having a top surface and a plurality of sides. A hermetic sealant is applied to each electronic device to completely encase the top surface and the sides while bonding to the base layer. At least one of the layers is a metallization layer formed by metal deposition. Full metallization may be applied over the entire wafer and a pattern subsequently transferred to the full metallization by one of laser and chemical etching. The electronic device may further include at least one electronic component attached to one of the layers and encased by the hermetic sealant.

Abstract: A hermetically sealed electronic device and method of fabrication are provided. A base layer of a wafer is created using a substrate formed from ultra-thin glass or ceramic using panel or roll to roll processing. One or more layers are bonded to the base layer. The wafer is singulated into a plurality of electronic devices having a top surface and a plurality of sides. A hermetic sealant is applied to each electronic device to completely encase the top surface and the sides while bonding to the base layer. At least one of the layers is a metallization layer formed by metal deposition. Full metallization may be applied over the entire wafer and a pattern subsequently transferred to the full metallization by one of laser and chemical etching. The electronic device may further include at least one electronic component attached to one of the layers and encased by the hermetic sealant.

Abstract: A hermetically sealed electronic device and method of fabrication are provided. A base layer of a wafer is created using a substrate formed from ultra-thin glass or ceramic using panel or roll to roll processing. One or more layers are bonded to the base layer. The wafer is singulated into a plurality of electronic devices having a top surface and a plurality of sides. A hermetic sealant is applied to each electronic device to completely encase the top surface and the sides while bonding to the base layer. At least one of the layers is a metallization layer formed by metal deposition. Full metallization may be applied over the entire wafer and a pattern subsequently transferred to the full metallization by one of laser and chemical etching. The electronic device may further include at least one electronic component attached to one of the layers and encased by the hermetic sealant.

Abstract: A hermetically sealed electronic device and method of fabrication are provided. A base layer of a wafer is created using a substrate formed from ultra-thin glass or ceramic using panel or roll to roll processing. One or more layers are bonded to the base layer. The wafer is singulated into a plurality of electronic devices having a top surface and a plurality of sides. A hermetic sealant is applied to each electronic device to completely encase the top surface and the sides while bonding to the base layer. At least one of the layers is a metallization layer formed by metal deposition. Full metallization may be applied over the entire wafer and a pattern subsequently transferred to the full metallization by one of laser and chemical etching. The electronic device may further include at least one electronic component attached to one of the layers and encased by the hermetic sealant.

Abstract: A device for use in a display system including an array of pixel cells formed on a substrate. Each pixel cell being coupled to at least one gate line of a plurality of gate lines formed on the substrate and at least one data line of a plurality of data lines being formed on the substrate. The device includes first and second transistors formed on the substrate. Each transistor has a gate electrode and first and second electrodes defining a serpentine channel region there between voltage applied to the gate electrode controls conductivity of the channel region. Preferably, a common electrode includes one of the first and second electrodes of the first transistor and one of the first and second electrodes of the second transistor.

Abstract: An improved apparatus for testing an array of pixel cells formed on a substrate is provided. Each pixel cell is coupled to at least one gate line of a plurality of gate lines formed on the substrate and at least one data line of a plurality of data lines formed on the substrate. The gate lines and/or data lines are partitioned into a plurality of groups. For each particular group, a first probe pad and select logic is formed on said substrate. The select logic, which is coupled between the first probe pad and the lines of the particular group, selectively couples the first probe pad to the lines of said particular group based upon first control signals supplied to the select logic during a test routine whereby charge is written to, stored, and read from the array of pixel cells. In addition, a second probe pad and hold logic for each particular group may be formed on the substrate.