Abstract: A logic output macrocell (30) is programmable to select between a registered output (38a-n) or a nonregistered output (42a-n). The selection between the two outputs can be either reversible through coupling to a selecting output (58) of a combinatorial logic matrix (12) or it can be permanently programmed with the aid of an architectural fuse (52a-n).

Abstract: A flip-flop circuit has two D type flip-flops. A common system clock drives both flip-flops. A stream of asynchronous data is connected to the data input of the first flip-flop FF1. The output of FF1 is connected to the data input of the second flip-flop FF2. The timing characteristics of FF1 and FF2 are chosen so that the time from the clock pulse to the high logic output of FF1 plus the set up time of FF2 is less than the minimum propagation delay time of FF2.

Abstract: A programmable sequence generator comprises a combinatorial logic matrix (10,12) and an on-chip timer (24) having count lines (26) coupled as inputs to the logic matrix (10). Combinatorial logic functions may be programmed into the matrix having as variables external inputs (14), a count number represented by the count lines (26) and internal inputs (48) fed back from outputs of the logic matrix (12). In a preferred embodiment, state registers (46) are provided, such that the programmable sequence generator can operate in any one of a plurality of different states. The programmable sequence generator can be configured as a waveform generator (92), a refresh timer (94) or a dynamic memory timing controller (96), among other programmable logic applications.