Abstract: A capacitor having improved size for enhanced capacitance and a method of forming the same are disclosed. In one embodiment, the capacitor is a stacked container capacitor used in a dynamic random access memory circuit. The capacitor provides a capacitor that has high storage capacitance which provides an increased efficiency for a cell without an increase in the size of the cell.

Abstract: A capacitor having improved size for enhanced capacitance and a method of forming the same are disclosed. In one embodiment, the capacitor is a stacked container capacitor used in a dynamic random access memory circuit. The capacitor provides a capacitor that has high storage capacitance which provides an increased efficiency for a cell without an increase in the size of the cell.

Abstract: A capacitor having improved size for enhanced capacitance and a method of forming the same are disclosed. In one embodiment, the capacitor is a stacked container capacitor used in a dynamic random access memory circuit. The capacitor provides a capacitor that has high storage capacitance which provides an increased efficiency for a cell without an increase in the size of the cell.

Abstract: Silicon nitride layers, having thicknesses of 100 angstroms or less, are formed using chemical vapor deposition (CVD). Higher pressure and lower temperature deposition regimes are used to provide more uniform step coverage on complex topographies, such as hemispherical grain polysilicon. In one embodiment, a hot wall batch CVD processing apparatus utilizes a processing chamber pressure of at least as high as approximately 500 mTorr to deposit such films. In a second embodiment, a single wafer cold wall CVD processing apparatus utilizes a processing chamber pressure of approximately 1 to 600 Torr to deposit such films. The temperature range used to process such films is approximately 400 to 700 degrees Celsius. A mixture of ammonia (NH3) and a silane gas, such as dichlorosilane (DCS), are reacted in any type of CVD apparatus to produce the films.

Abstract: A capacitor having improved size for enhanced capacitance and a method of forming the same are disclosed. In one embodiment, the capacitor is a stacked container capacitor used in a dynamic random access memory circuit. The capacitor provides a capacitor that has high storage capacitance which provides an increased efficiency for a cell without an increase in the size of the cell.

Abstract: A capacitor having improved size for enhanced capacitance and a method of forming the same are disclosed. In one embodiment, the capacitor is a stacked container capacitor used in a dynamic random access memory circuit. The capacitor provides a capacitor that has high storage capacitance which provides an increased efficiency for a cell without an increase in the size of the cell.

Abstract: In one aspect, the invention includes a semiconductor processing method of selectively reducing an etch rate of a doped material. At least some dopant is removed from one portion of the doped material while leaving the dopant in an other portion of the doped material. In another aspect, the invention includes a semiconductor processing method of forming openings. A doped material is provided over a substrate. Openings are etched in the doped material. Dopant in the doped material proximate the openings is depleted relative to other regions of the doped material. In yet another aspect, the invention includes a semiconductor processing method of forming openings. A doped material is provided over a substrate and openings are formed in the doped material. The doped material has a substantially uniform dopant concentration throughout its thickness. One peripheral portion of the openings is defined by the doped material and another peripheral portion is defined by another material.

Abstract: A method is provided for fabricating a nitride layer of the semiconductor integrated circuit on a semiconductor substrate in a processing chamber. Source gases are applied to the processing chamber and a first nitride layer is deposited over the semiconductor substrate according to the source gases. The source gases are discontinued and the processing chamber is pumped out. Source gases are again applied to the processing chamber and a second nitride layer is deposited upon the first nitride layer according to the applied source gases. The first and second nitride layers form a combined nitride layer. Four alternate embodiments are set forth. In the first embodiment a predetermined amount of time is waited between the pumpout of the processing chamber and the deposition of the second nitride layer. The amount of time can be approximately ten minutes. In the second embodiment, the processing chamber is purged with nitrogen gas prior to depositing the second nitride layer.