Abstract: In carrier and timing recovery systems for high performance data modems it is essential to employ threshold comparators and to be able to determine accurately zero-crossing instants. The circuit of the invention comprises a comparator with feedback which produces a positive transition of the comparator output in response to the negative zero-crossing transition of the input signal on condition that the previous half-cycle of the input signal has exceeded the positive reference threshold. In a practical arrangement two comparators are provided together with a pair of bistable storage elements which produces a narrow pulse in response to the negative zero-crossing transition of an input signal provided that the input signal has exceeded the positive reference threshold applied to the second comparator.