Patents by Inventor Robert K. Grubbs

Robert K. Grubbs has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11980108
    Abstract: Techniques are described to form a liner to protect a material, such as a storage element material, from damage during subsequent operations or phases of a manufacturing process. The liner may be bonded to the material (e.g., a chalcogenide material) using a strong bond or a weak bond. In some cases, a sealant material may be deposited during an etching phase of the manufacturing process to prevent subsequent etching operations from damaging a material that has just been etched.
    Type: Grant
    Filed: August 4, 2022
    Date of Patent: May 7, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Farrell M. Good, Robert K. Grubbs, Gurpreet S. Lugani
  • Publication number: 20230023105
    Abstract: Techniques are described to form a liner to protect a material, such as a storage element material, from damage during subsequent operations or phases of a manufacturing process. The liner may be bonded to the material (e.g., a chalcogenide material) using a strong bond or a weak bond. In some cases, a sealant material may be deposited during an etching phase of the manufacturing process to prevent subsequent etching operations from damaging a material that has just been etched.
    Type: Application
    Filed: August 4, 2022
    Publication date: January 26, 2023
    Inventors: Farrell M. Good, Robert K. Grubbs, Gurpreet S. Lugani
  • Patent number: 11551926
    Abstract: A method of forming a microelectronic device comprises treating a base structure with a first precursor to adsorb the first precursor to a surface of the base structure and form a first material. The first precursor comprises a hydrazine-based compound including Si—N—Si bonds. The first material is treated with a second precursor to covert the first material into a second material. The second precursor comprises a Si-centered radical. The second material is treaded with a third precursor to covert the second material into a third material comprising Si and N. The third precursor comprises an N-centered radical. An ALD system and a method of forming a seal material through ALD are also described.
    Type: Grant
    Filed: January 22, 2021
    Date of Patent: January 10, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Farrell M. Good, Robert K. Grubbs
  • Publication number: 20220376176
    Abstract: An electronic device comprising a stack structure comprising one or more stacks of materials and a metal oxide material adjacent to the stacks of materials. The materials of the stacks comprise one or more chalcogenide materials. The metal oxide material comprises aluminum oxide, aluminum silicate, hafnium oxide, hafnium silicate, zirconium oxide, zirconium silicate, or a combination thereof and the metal oxide material extends continuously from an upper portion of the one or more stacks of materials to a lower portion of the one or more stacks of materials. Additional electronic devices are disclosed, as are related systems and methods of forming an electronic device.
    Type: Application
    Filed: August 8, 2022
    Publication date: November 24, 2022
    Inventors: Santanu Sarkar, Robert K. Grubbs, Farrell M. Good, Adam W. Saxler, Andrea Gotti
  • Patent number: 11444243
    Abstract: An electronic device comprising a stack structure comprising one or more stacks of materials and a metal oxide material adjacent to the stacks of materials. The materials of the stacks comprise one or more chalcogenide materials. The metal oxide material comprises aluminum oxide, aluminum silicate, hafnium oxide, hafnium silicate, zirconium oxide, zirconium silicate, or a combination thereof and the metal oxide material extends continuously from an upper portion of the one or more stacks of materials to a lower portion of the one or more stacks of materials. Additional electronic devices are disclosed, as are related systems and methods of forming an electronic device.
    Type: Grant
    Filed: October 28, 2019
    Date of Patent: September 13, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Santanu Sarkar, Robert K. Grubbs, Farrell M. Good, Adam W. Saxler, Andrea Gotti
  • Patent number: 11417840
    Abstract: Techniques are described to form a liner to protect a material, such as a storage element material, from damage during subsequent operations or phases of a manufacturing process. The liner may be bonded to the material (e.g., a chalcogenide material) using a strong bond or a weak bond. In some cases, a sealant material may be deposited during an etching phase of the manufacturing process to prevent subsequent etching operations from damaging a material that has just been etched.
    Type: Grant
    Filed: December 31, 2019
    Date of Patent: August 16, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Farrell M. Good, Robert K. Grubbs, Gurpreet S. Lugani
  • Publication number: 20220238324
    Abstract: A method of forming a microelectronic device comprises treating a base structure with a first precursor to adsorb the first precursor to a surface of the base structure and form a first material. The first precursor comprises a hydrazine-based compound including Si—N—Si bonds. The first material is treated with a second precursor to covert the first material into a second material. The second precursor comprises a Si-centered radical. The second material is treaded with a third precursor to covert the second material into a third material comprising Si and N. The third precursor comprises an N-centered radical. An ALD system and a method of forming a seal material through ALD are also described.
    Type: Application
    Filed: January 22, 2021
    Publication date: July 28, 2022
    Inventors: Farrell M. Good, Robert K. Grubbs
  • Publication number: 20220020662
    Abstract: Methods, systems, and devices related to a memory device with a thermal barrier are described. The thermal barrier (e.g., a low density thermal barrier) may be positioned between an access line (e.g., a digit line or a word line) and a cell component. The thermal barrier may be formed on the surface of a barrier material by applying a plasma treatment to the barrier material. The thermal barrier may have a lower density than the barrier material and may be configured to thermally insulate the cell component from thermal energy generated in the memory device, among other benefits.
    Type: Application
    Filed: October 1, 2021
    Publication date: January 20, 2022
    Inventors: Pengyuan Zheng, David Ross Economy, Yongjun J. Hu, Kent H. Zhuang, Robert K. Grubbs
  • Patent number: 11158561
    Abstract: Methods, systems, and devices related to a memory device with a thermal barrier are described. The thermal barrier (e.g., a low density thermal barrier) may be positioned between an access line (e.g., a digit line or a word line) and a cell component. The thermal barrier may be formed on the surface of a barrier material by applying a plasma treatment to the barrier material. The thermal barrier may have a lower density than the barrier material and may be configured to thermally insulate the cell component from thermal energy generated in the memory device, among other benefits.
    Type: Grant
    Filed: May 1, 2019
    Date of Patent: October 26, 2021
    Inventors: Pengyuan Zheng, David Ross Economy, Yongjun J. Hu, Kent H. Zhuang, Robert K. Grubbs
  • Publication number: 20210296582
    Abstract: An oxidation barrier for non-volatile memory with materials sensitive to temperature and/or cross contamination (e.g., chalcogenide materials) are described The barrier can be formed, for example, around the boundaries of a non-volatile memory tile (also known as a block or sub-array). For example, a non-volatile memory device can include an oxidation barrier on a side wall of a trench between adjacent memory tiles.
    Type: Application
    Filed: June 7, 2021
    Publication date: September 23, 2021
    Inventors: Kevin L. BAKER, Robert K. GRUBBS, Farrell M. GOOD, Ervin T. HILL, Bhumika CHHABRA, Jay S. BROWN
  • Patent number: 11069855
    Abstract: An oxidation barrier for non-volatile memory with materials sensitive to temperature and/or cross contamination (e.g., chalcogenide materials) are described The barrier can be formed, for example, around the boundaries of a non-volatile memory tile (also known as a block or sub-array). For example, a non-volatile memory device can include an oxidation barrier on a side wall of a trench between adjacent memory tiles.
    Type: Grant
    Filed: July 1, 2019
    Date of Patent: July 20, 2021
    Assignee: Intel Corporation
    Inventors: Kevin L. Baker, Robert K. Grubbs, Farrell M. Good, Ervin T. Hill, Bhumika Chhabra, Jay S. Brown
  • Patent number: 11053601
    Abstract: A method for electroplating a nonmetallic grating including providing a nonmetallic grating; performing an atomic layer deposition (ALD) reaction to form a seed layer on the nonmetallic grating; and electroplating a metallic layer on the seed layer such that the metallic layer uniformly and conformally coats the nonmetallic grating. An apparatus including a silicon substrate having gratings with an aspect-ratio of at least 20:1; a atomic layer deposition (ALD) seed layer formed on the gratings; and an electroplated metallic layer formed on the seed layer, wherein the electroplated metallic layer uniformly and conformally coats the gratings.
    Type: Grant
    Filed: October 30, 2018
    Date of Patent: July 6, 2021
    Assignee: National Technology & Engineering Solutions of Sandia, LLC
    Inventors: Adam M. Rowen, Robert K. Grubbs, Jonathan Joseph Coleman
  • Publication number: 20210202841
    Abstract: Techniques are described to form a liner to protect a material, such as a storage element material, from damage during subsequent operations or phases of a manufacturing process. The liner may be bonded to the material (e.g., a chalcogenide material) using a strong bond or a weak bond. In some cases, a sealant material may be deposited during an etching phase of the manufacturing process to prevent subsequent etching operations from damaging a material that has just been etched.
    Type: Application
    Filed: December 31, 2019
    Publication date: July 1, 2021
    Inventors: Farrell M. Good, Robert K. Grubbs, Gurpreet S. Lugani
  • Publication number: 20210126193
    Abstract: An electronic device comprising a stack structure comprising one or more stacks of materials and a metal oxide material adjacent to the stacks of materials. The materials of the stacks comprise one or more chalcogenide materials. The metal oxide material comprises aluminum oxide, aluminum silicate, hafnium oxide, hafnium silicate, zirconium oxide, zirconium silicate, or a combination thereof and the metal oxide material extends continuously from an upper portion of the one or more stacks of materials to a lower portion of the one or more stacks of materials. Additional electronic devices are disclosed, as are related systems and methods of forming an electronic device.
    Type: Application
    Filed: October 28, 2019
    Publication date: April 29, 2021
    Inventors: Santanu Sarkar, Robert K. Grubbs, Farrell M. Good, Adam W. Saxler, Andrea Gotti
  • Publication number: 20210005810
    Abstract: An oxidation barrier for non-volatile memory with materials sensitive to temperature and/or cross contamination (e.g., chalcogenide materials) are described The barrier can be formed, for example, around the boundaries of a non-volatile memory tile (also known as a block or sub-array). For example, a non-volatile memory device can include an oxidation barrier on a side wall of a trench between adjacent memory tiles.
    Type: Application
    Filed: July 1, 2019
    Publication date: January 7, 2021
    Inventors: Kevin L. BAKER, Robert K. GRUBBS, Farrell M. GOOD, Ervin T. HILL, Bhumika CHHABRA, Jay S. BROWN
  • Publication number: 20200350226
    Abstract: Methods, systems, and devices related to a memory device with a thermal barrier are described. The thermal barrier (e.g., a low density thermal barrier) may be positioned between an access line (e.g., a digit line or a word line) and a cell component. The thermal barrier may be formed on the surface of a barrier material by applying a plasma treatment to the barrier material. The thermal barrier may have a lower density than the barrier material and may be configured to thermally insulate the cell component from thermal energy generated in the memory device, among other benefits.
    Type: Application
    Filed: May 1, 2019
    Publication date: November 5, 2020
    Inventors: Pengyuan Zheng, David Ross Economy, Yongjun J. Hu, Kent H. Zhuang, Robert K. Grubbs
  • Patent number: 10262931
    Abstract: The present invention relates to a lateral via to provide an electrical connection to a buried conductor. In one instance, the buried conductor is a through via that extends along a first dimension, and the lateral via extends along a second dimension that is generally orthogonal to the first dimension. In another instance, the second dimension is oblique to the first dimension. Components having such lateral vias, as well as methods for creating such lateral vias are described herein.
    Type: Grant
    Filed: May 15, 2018
    Date of Patent: April 16, 2019
    Assignees: National Technology & Engineering Solutions of Sandia, LLC, Varioscale, Inc.
    Inventors: David P. Adams, Kira L. Fishgrab, Karl Douglas Greth, Michael David Henry, Jeffrey Stevens, V. Carter Hodges, Randy J. Shul, Ronald S. Goeke, Robert K. Grubbs, Scott Silverman
  • Publication number: 20190074100
    Abstract: A method for electroplating a nonmetallic grating including providing a nonmetallic grating; performing an atomic layer deposition (ALD) reaction to form a seed layer on the nonmetallic grating; and electroplating a metallic layer on the seed layer such that the metallic layer uniformly and conformally coats the nonmetallic grating. An apparatus including a silicon substrate having gratings with an aspect-ratio of at least 20:1; a atomic layer deposition (ALD) seed layer formed on the gratings; and an electroplated metallic layer formed on the seed layer, wherein the electroplated metallic layer uniformly and conformally coats the gratings.
    Type: Application
    Filed: October 30, 2018
    Publication date: March 7, 2019
    Inventors: Adam M. Rowen, Robert K. Grubbs, Jonathan Joseph Coleman
  • Patent number: 10147510
    Abstract: A method for electroplating a nonmetallic grating including providing a nonmetallic grating; performing an atomic layer deposition (ALD) reaction to form a seed layer on the nonmetallic grating; and electroplating a metallic layer on the seed layer such that the metallic layer uniformly and conformally coats the nonmetallic grating. An apparatus including a silicon substrate having gratings with an aspect-ratio of at least 20:1; a atomic layer deposition (ALD) seed layer formed on the gratings; and an electroplated metallic layer formed on the seed layer, wherein the electroplated metallic layer uniformly and conformally coats the gratings.
    Type: Grant
    Filed: November 15, 2013
    Date of Patent: December 4, 2018
    Assignee: National Technology & Engineering Solutions of Sandia, LLC
    Inventors: Adam M. Rowen, Robert K. Grubbs, Jonathan Joseph Coleman
  • Publication number: 20180269143
    Abstract: The present invention relates to a lateral via to provide an electrical connection to a buried conductor. In one instance, the buried conductor is a through via that extends along a first dimension, and the lateral via extends along a second dimension that is generally orthogonal to the first dimension. In another instance, the second dimension is oblique to the first dimension. Components having such lateral vias, as well as methods for creating such lateral vias are described herein.
    Type: Application
    Filed: May 15, 2018
    Publication date: September 20, 2018
    Inventors: David P. Adams, Kira L. Fishgrab, Karl Douglas Greth, Michael David Henry, Jeffrey Stevens, V. Carter Hodges, Randy J. Shul, Ronald S. Goeke, Robert K. Grubbs, Scott Silverman