Abstract: A time to digital converter includes a sample module operable to sample an input signal at multiple different instances of time. A transition detection module, formed of comparison elements, processes the sampled input signal at successive time instances so as to detect transitions in the input signal in terms of time. An output module generates detected transitions in the input signal on multiple parallel outputs.

Abstract: A pixel circuit includes a single photon avalanche diode (SPAD) and a measurement circuit including a capacitance. The SPAD detects an incident photon and the measurement circuit discharges the capacitance at a known rate during a discharge time period. The length of the discharge time period is determined by the time of detection of the photon, such that the final amount of charge on the capacitance corresponds to the time of flight of the photon. The pixel circuit may be included in a time resolved imaging apparatus. A method of measuring the time of flight of a photon includes responding to an incident photon detection by discharging a capacitance at a known rate and correlating final capacitance charge to time of flight.

Abstract: A time to digital converter includes a sample module operable to sample an input signal at multiple different instances of time. A transition detection module, formed of comparison elements, processes the sampled input signal at successive time instances so as to detect transitions in the input signal in terms of time. An output module generates detected transitions in the input signal on multiple parallel outputs.

Abstract: A deep SPAD structure uses the substrate as the anode terminal of its multiplication p-n junction. A bias voltage for the SPAD (in excess of the SPAD's breakdown voltage) is coupled to the SPAD's cathode terminal. The bias voltage is generated by a charge pump circuit which is also integrated on the substrate. The charge pump circuit is configured to isolate the bias voltage on the cathode terminal. A triple well CMOS process is used to isolate the transistors of the charge pump circuit from the substrate.

Abstract: A pixel circuit includes a single photon avalanche diode (SPAD) and a measurement circuit including a capacitance. The SPAD detects an incident photon and the measurement circuit discharges the capacitance at a known rate during a discharge time period. The length of the discharge time period is determined by the time of detection of the photon, such that the final amount of charge on the capacitance corresponds to the time of flight of the photon. The pixel circuit may be included in a time resolved imaging apparatus. A method of measuring the time of flight of a photon includes responding to an incident photon detection by discharging a capacitance at a known rate and correlating final capacitance charge to time of flight.

Abstract: A CMOS single photon avalanche diode (SPAD) design uses conventional, or at least known, CMOS processes to produce a device having a breakdown region in which the main p-n junction is formed of a deep n-well layer, and optionally on the other side, a p-add layer. The SPAD may also have a guard ring region which comprises the p-epi layer without any implant. The SPAD may have curved or circular perimeters. A CMOS chip comprises SPADs as described and other NMOS devices all sharing the same deep n-well.

Abstract: A CMOS single photon avalanche diode (SPAD) design uses conventional, or at least known, CMOS processes to produce a device having a breakdown region in which the main p-n junction is formed of a deep n-well layer, and optionally on the other side, a p-add layer. The SPAD may also have a guard ring region which comprises the p-epi layer without any implant. The SPAD may have curved or circular perimeters. A CMOS chip comprises SPADs as described and other NMOS devices all sharing the same deep n-well.

Abstract: A CMOS single photon avalanche diode (SPAD) design uses conventional, or at least known, CMOS processes to produce a device having a breakdown region in which the main p-n junction is formed of a deep n-well layer, and optionally on the other side, a p-add layer. The SPAD may also have a guard ring region which comprises the p-epi layer without any implant. The SPAD may have curved or circular perimeters. A CMOS chip comprises SPADs as described and other NMOS devices all sharing the same deep n-well.

Abstract: A programmable gain amplifier (PGA) system comprises selectable parallel transconductors in a front end, independently selectable serial amplification circuits in a back end. The back end is configured to receive an output of the front end and may include a plurality of current or voltage mode amplifiers in series. The PGA system also includes control circuitry to select a gain configuration for the PGA by selecting selectable components in the front and back ends. The PGA system may additionally include control circuitry configured to change the transconductance of one or more of the front end transconductors such that the gain configurations of the PGA are independent of variations such as those due to temperature and fabrication. The PGA system may be used between a signal receiver and an analog to digital converter.

Abstract: A programmable gain amplifier comprising alternatively selectable parallel circuits in a front end and independently selectable serial amplification circuits in a back end. The front end may include, for example, a plurality of transconductors in parallel and each configured to generate a current proportional to a received voltage. A ratio of the generated current to the received voltage being different for each of the transconductors. The back end is configured to receive an output of a selected member of the parallel circuits and may include a plurality of current or voltage mode amplifiers in series. For example, the back end may include a plurality of current-mode gain stages and switches configured to control which of the current-mode gain stages are used to amplify the output of the front end. The programmable gain amplifier may be used between a signal receiver and an analog to digital converter.

Abstract: A programmable gain amplifier (PGA) system comprises selectable parallel transconductors in a front end, independently selectable serial amplification circuits in a back end. The back end is configured to receive an output of the front end and may include a plurality of current or voltage mode amplifiers in series. The PGA system also includes control circuitry to select a gain configuration for the PGA by selecting selectable components in the front and back ends. The PGA system may additionally include control circuitry configured to change the transconductance of one or more of the front end transconductors such that the gain configurations of the PGA are independent of variations such as those due to temperature and fabrication. The PGA system may be used between a signal receiver and an analog to digital converter.

Abstract: A programmable gain amplifier (PGA) system comprises selectable parallel transconductors in a front end, independently selectable serial amplification circuits in a back end. The back end is configured to receive an output of the front end and may include a plurality of current or voltage mode amplifiers in series. The PGA system also includes control circuitry to select a gain configuration for the PGA by selecting selectable components in the front and back ends. The PGA system may additionally include control circuitry configured to change the transconductance of one or more of the front end transconductors such that the gain configurations of the PGA are independent of variations such as those due to temperature and fabrication. The PGA system may be used between a signal receiver and an analog to digital converter.

Abstract: A programmable gain amplifier comprising alternatively selectable parallel circuits in a front end and independently selectable serial amplification circuits in a back end. The front end may include, for example, a plurality of transconductors in parallel and each configured to generate a current proportional to a received voltage. A ratio of the generated current to the received voltage being different for each of the transconductors. The back end is configured to receive an output of a selected member of the parallel circuits and may include a plurality of current or voltage mode amplifiers in series. For example, the back end may include a plurality of current-mode gain stages and switches configured to control which of the current-mode gain stages are used to amplify the output of the front end. The programmable gain amplifier may be used between a signal receiver and an analog to digital converter.

Abstract: A programmable gain amplifier comprising alternatively selectable parallel circuits in a front end and independently selectable serial amplification circuits in a back end. The front end may include, for example, a plurality of transconductors in parallel and each configured to generate a current proportional to a received voltage. A ratio of the generated current to the received voltage being different for each of the transconductors. The back end is configured to receive an output of a selected member of the parallel circuits and may include a plurality of current or voltage mode amplifiers in series. For example, the back end may include a plurality of current-mode gain stages and switches configured to control which of the current-mode gain stages are used to amplify the output of the front end. The programmable gain amplifier may be used between a signal receiver and an analog to digital converter.

Abstract: A programmable gain amplifier (PGA) system comprises selectable parallel transconductors in a front end, independently selectable serial amplification circuits in a back end. The back end is configured to receive an output of the front end and may include a plurality of current or voltage mode amplifiers in series. The PGA system also includes control circuitry to select a gain configuration for the PGA by selecting selectable components in the front and back ends. The PGA system may additionally include control circuitry configured to change the transconductance of one or more of the front end transconductors such that the gain configurations of the PGA are independent of variations such as those due to temperature and fabrication. The PGA system may be used between a signal receiver and an analog to digital converter.

Abstract: A programmable gain amplifier comprising alternatively selectable parallel circuits in a front end and independently selectable serial amplification circuits in a back end. The front end may include, for example, a plurality of transconductors in parallel and each configured to generate a current proportional to a received voltage. A ratio of the generated current to the received voltage being different for each of the transconductors. The back end is configured to receive an output of a selected member of the parallel circuits and may include a plurality of current or voltage mode amplifiers in series. For example, the back end may include a plurality of current-mode gain stages and switches configured to control which of the current-mode gain stages are used to amplify the output of the front end. The programmable gain amplifier may be used between a signal receiver and an analog to digital converter.

Abstract: A CMOS single photon avalanche diode (SPAD) design uses conventional, or at least known, CMOS processes to produce a device having a breakdown region in which the main p-n junction is formed of a deep n-well layer, and optionally on the other side, a p-add layer. The SPAD may also have a guard ring region which comprises the p-epi layer without any implant. The SPAD may have curved or circular perimeters. A CMOS chip comprises SPADs as described and other NMOS devices all sharing the same deep n-well.

Abstract: A resistor-input transconductor includes a circuit configured to generate a common-mode compensation current. The common-mode compensation current is used to compensate for the common-mode voltage of the inputs. A current output of the resistor-input transconductor is proportional to a voltage difference between the two inputs and essentially independent of a common-mode voltage of the two inputs. The resistor input transconductor may be applied in a variety of applications including, for example, communications.

Abstract: A photomask and method for evaluating an initial calibration for a scanning electron microscope are disclosed. The method includes generating an initial calibration for a SEM that contains a target width for a feature on a reference target and measuring the feature on the reference target in the SEM to determine a measured width for the feature. The measured width is compared to the target width to generate a shift deviation and a current calibration for the SEM is adjusted based on the shift deviation.