Abstract: An implant delivery device may include an implant holding portion proximate the distal end, the implant holding portion being configured to retain a sheet-like implant during implantation of the implant. In addition, the implant holding portion may be configured to receive the implant with a fixed implant supporting flange member configured to support the implant on one side, and a movable implant supporting flange member. The movable implant supporting flange member may be configured to be slidable between a distal position and a proximal position, wherein, in the distal position, the movable implant supporting flange member and secures the implant against the fixed implant supporting flange member, and in the proximal position, the movable implant supporting flange member is withdrawn from the distal end of the implant delivery device, thus enabling release of the implant.

Abstract: A fused tap for an elbow connector that properly insulates and houses an interruption device or fuse to provide protection on underground distribution power lines. The interruption device is replaceable without the need of replacing the entire assembly. The fused tap provides flexibility in installation for existing and new underground distribution lines and/or feeders.

Abstract: A fused tap for an elbow connector that properly insulates and houses an interruption device or fuse to provide protection on underground distribution power lines. The interruption device is replaceable without the need of replacing the entire assembly. The fused tap provides flexibility in installation for existing and new underground distribution lines and/or feeders.

Abstract: A fused tap for an elbow connector that properly insulates and houses an interruption device or fuse to provide protection on underground distribution power lines. The interruption device is replaceable without the need of replacing the entire assembly. The fused tap provides flexibility in installation for existing and new underground distribution lines and/or feeders.

Abstract: An FET comprising as many as three parallel channels having different threshold voltages. The two outer channels can have very low W/L ratios and resulting low drain-to-source currents. In one embodiment, the FET has a central enhancement channel flanked by low W/L ratio, low current, depletion channels. The FET is fabricated by forming an oxide mask (e.g., by etching a window in the gate oxide over the device active area); enhancement implanting the substrate through the window (e.g., n-substrate and n-implant for a p-channel FET); enlarging the window width a predetermined distance by etching; and depletion implanting the substrate through the window (p-implant for n-substrate) to a concentration below that of the enhancement implant. The gate structure is formed over the combined enhancement and depletion channels and a source and a drain span the ends of the channels. This effectively provides an enhancement FET which is in parallel with a depletion FET.

Abstract: An FET comprising as many as three parallel channels having different threshold voltages. The two outer channels can have very low W/L ratios and resulting low drain-to-source currents. In one embodiment, the FET has a central enhancement channel flanked by low W/L ratio, low current, depletion channels. The FET is fabricated by forming an oxide mask (e.g., by etching a window in the gate oxide over the device active area); enhancement implanting the substrate through the window (e.g., n-substrate and n-implant for a p-channel FET); enlarging the window width a predetermined distance by etching; and depletion implanting the substrate through the window (p-implant for n-substrate) to a concentration below that of the enhancement implant. The gate structure is formed over the combined enhancement and depletion channels and a source and a drain span the ends of the channels. This effectively provides an enhancement FET which is in parallel with a depletion FET.

Abstract: A method of manufacturing a silicon gate MIS device using ion implantation and controlled ion scattering to provide concurrent formation and automatic alignment of the gate structure and adjacent impurity regions. In a preferred embodiment, the process is for the gate structure and source and drain of silicon gate FETs. The layered gate constituents--typically oxide and silicon--are formed on a semiconductor wafer. A photoresist mask which is larger than the desired gate size is formed on the silicon and the silicon is etched to the predetermined gate size beneath the overhanging mask. The photoresist mask is then used during ion implantation of the source and drain to establish the lateral surface boundaries within which ions are implanted. These lateral surface boundaries are selected so that as the ions are driven into the substrate to the desired junction depth of the source and drain by lateral scattering, the source and drain are aligned with the silicon gate electrode.

Abstract: A method for making an FET comprising as many as three parallel channels having different threshold voltages. The two outer channels can have very low W/L ratios and resulting low drain-to-source currents. In one embodiment, the FET has a central enhancement channel flanked by low W/L ratio, low current, depletion channels. This FET is fabricated by (1) forming on the field oxide a photoresist mask having a relatively narrow aperture; (2) overetching the field oxide beneath the photoresist mask aperture to form a relatively wide aperture in the field oxide, leaving a photoresist overhang; (3) implanting the substrate through the relatively narrow photoresist mask aperture to provide an enhancement section of the channel region; (4) removing the photoresist mask; and (5) depletion implanting the substrate through the relatively wide field oxide aperture. The gate structure is formed over the combined enhancement and depletion channels and a source and a drain span the ends of the channels.

Abstract: A read-only memory is manufactured from a matrix or array of multilayer electrical devices, each of which includes at least one metallic layer, a portion of which contacts a doped semi conductor region. The metallic layers are controllably and rapidly thinned down and decreased in cross-sectional area in the vicinity of the doped regions to form fusible links, thus producing a ROM starting product. Fusible link formation is enhanced by the use of an etchant for the metallic layer which forms an electrochemical cell in conjunction therewith and with the semiconductor and the doped region. Any metallic layers not contacting a doped region are also etched by the etchant, but at the much slower "chemical rate". Following the production of the starting product, a ROM may be produced by the selective application of voltages to selected fusible links, the I.sup.2 R heating of the links fusing them, or blowing them out. In a preferred embodiment, the electrical devices are MOSFETS.