Abstract: Structures including an edge coupler and methods of fabricating a structure including an edge coupler. The structure includes a waveguide core region on a first dielectric layer, and a second dielectric layer on the waveguide core region and the first dielectric layer. The waveguide core region has a tapered section with an end surface that terminates adjacent to an edge of the first dielectric layer. The second dielectric layer includes a first trench and a second trench that are each positioned adjacent to the tapered section of the waveguide core region.

Abstract: Structures for an edge coupler of a photonics chip and methods of forming an edge coupler for a photonics chip. The structure includes a waveguide core on a dielectric layer, as well as an interconnect structure including a interlayer dielectric layer positioned over the dielectric layer and an opening penetrating through the interlayer dielectric layer to the waveguide core. A region of the interlayer dielectric layer is positioned to overlap with a portion of the waveguide core. The region of the interlayer dielectric layer has a surface that is rounded with a curvature.

Abstract: Structures for an edge coupler of a photonics chip and methods of forming an edge coupler for a photonics chip. The structure includes a waveguide core on a dielectric layer, as well as an interconnect structure including a interlayer dielectric layer positioned over the dielectric layer and an opening penetrating through the interlayer dielectric layer to the waveguide core. A region of the interlayer dielectric layer is positioned to overlap with a portion of the waveguide core. The region of the interlayer dielectric layer has a surface that is rounded with a curvature.

Abstract: Structures including an edge coupler and methods of fabricating a structure including an edge coupler. The structure includes a waveguide core region on a first dielectric layer, and a second dielectric layer on the waveguide core region and the first dielectric layer. The waveguide core region has a tapered section with an end surface that terminates adjacent to an edge of the first dielectric layer. The second dielectric layer includes a first trench and a second trench that are each positioned adjacent to the tapered section of the waveguide core region.

Abstract: A dual bond pad structure for a wafer with laser die attachment and methods of manufacture are disclosed. The method includes forming a bonding layer on a surface of a substrate. The method further includes forming solder bumps on the bonding layer. The method further includes patterning the bonding layer to form bonding pads some of which comprise the solder bumps thereon. The method further includes attaching a laser diode to selected bonding pads using solder connections formed on the laser diode. The method further includes attaching an interposer substrate to the solder bumps formed on the bonding pads.

Abstract: A dual bond pad structure for a wafer with laser die attachment and methods of manufacture are disclosed. The method includes forming a bonding layer on a surface of a substrate. The method further includes forming solder bumps on the bonding layer. The method further includes patterning the bonding layer to form bonding pads some of which comprise the solder bumps thereon. The method further includes attaching a laser diode to selected bonding pads using solder connections formed on the laser diode. The method further includes attaching an interposer substrate to the solder bumps formed on the bonding pads.

Abstract: A dual bond pad structure for a wafer with laser die attachment and methods of manufacture are disclosed. The method includes forming a bonding layer on a surface of a substrate. The method further includes forming solder bumps on the bonding layer. The method further includes patterning the bonding layer to form bonding pads some of which comprise the solder bumps thereon. The method further includes attaching a laser diode to selected bonding pads using solder connections formed on the laser diode. The method further includes attaching an interposer substrate to the solder bumps formed on the bonding pads.

Abstract: A dual bond pad structure for a wafer with laser die attachment and methods of manufacture are disclosed. The method includes forming a bonding layer on a surface of a substrate. The method further includes forming solder bumps on the bonding layer. The method further includes patterning the bonding layer to form bonding pads some of which comprise the solder bumps thereon. The method further includes attaching a laser diode to selected bonding pads using solder connections formed on the laser diode. The method further includes attaching an interposer substrate to the solder bumps formed on the bonding pads.

Abstract: Various aspects include an integrated circuit (IC), design structure, and a method of making the same. In one embodiment, the IC includes: a substrate; a dielectric layer disposed on the substrate; a set of wire components disposed on the dielectric layer, the set of wire components including a first wire component disposed proximate a second wire component; a bond pad disposed on the first wire component, the bond pad including an exposed portion; a passivation layer disposed on the dielectric layer about a portion of the bond pad and the set of wire components, the passivation layer defining a wire structure via connected to the second wire component; and a wire structure disposed on the passivation layer proximate the bond pad and connected to the second wire component through the wire structure via.

Abstract: Various aspects include an integrated circuit (IC), design structure, and a method of making the same. In one embodiment, the IC includes: a substrate; a dielectric layer disposed on the substrate; a set of wire components disposed on the dielectric layer, the set of wire components including a first wire component disposed proximate a second wire component; a bond pad disposed on the first wire component, the bond pad including an exposed portion; a passivation layer disposed on the dielectric layer about a portion of the bond pad and the set of wire components, the passivation layer defining a wire structure via connected to the second wire component; and a wire structure disposed on the passivation layer proximate the bond pad and connected to the second wire component through the wire structure via.

Abstract: An integrated waveguide structure with perforated chip edge seal and methods of manufacture are disclosed herein. The structure includes a guard ring structure surrounding an active region of an integrated circuit chip. The structure further includes a gap in the guard ring structure which is located at a predetermined level of the integrated circuit chip. The structure further includes a waveguide structure formed on a substrate of the integrated circuit chip. The structure further includes a fiber optic optically coupled to the waveguide structure through the gap formed in the guard ring structure.

Abstract: An integrated circuit (IC), design structure, and a method of making the same. In one embodiment, the IC includes: a substrate; a dielectric layer disposed on the substrate; a set of wire components disposed on the dielectric layer, the set of wire components including a first wire component disposed proximate a second wire component; a bond pad disposed on the first wire component, the bond pad including an exposed portion; a passivation layer disposed on the dielectric layer about a portion of the bond pad and the set of wire components, the passivation layer defining a wire structure via connected to the second wire component; and a wire structure disposed on the passivation layer proximate the bond pad and connected to the second wire component through the wire structure via.

Abstract: The disclosure relates to semiconductor structures and, more particularly, to barrier structures for underfill blockout regions uses in phonotics chip packaging and methods of manufacture. The structure includes a substrate with a plurality of solder connections and at least one optical fiber interface disposed within at least one cavity of the substrate. The structure further includes a barrier structure formed about the cavity which is structured to prevent underfill material from degrading an optical coupling of the optical fiber.

Abstract: The disclosure relates to semiconductor structures and, more particularly, to structures for preventing dicing damage on photonics wafers. The structure includes: an optical waveguide structure to optical fiber interface formed on an integrated circuit; and a groove formed in a substrate and which includes a structure preventing a fluid pressure of a dicing operation from damaging the substrate along the groove.

Abstract: Disclosed are multi-chip modules (MCMs) that allow for chip-to-chip transmission of light signals. The MCMs can incorporate at least two components, which are attached (e.g., by interconnects). For example, in one MCM disclosed herein, the two components can be an integrated circuit chip and an interposer to which the integrated circuit chip and one or more additional integrated circuit chips are attached by interconnects. In another MCM disclosed herein, the two components can be two integrated circuit chips that are stacked and attached to each other by interconnects. In either case, the two components can each have a waveguide and a grating coupler coupled to one end of the waveguide. The grating couplers on the different components can be approximately vertically aligned, thereby allowing light signals to be transmitted between the waveguides on those different components. Also, disclosed herein are methods of forming such MCMs.

Abstract: The disclosure relates to semiconductor structures and, more particularly, to barrier structures for underfill blockout regions uses in phonotics chip packaging and methods of manufacture. The structure includes a substrate with a plurality of solder connections and at least one optical fiber interface disposed within at least one cavity of the substrate. The structure further includes a barrier structure formed about the cavity which is structured to prevent underfill material from degrading an optical coupling of the optical fiber.

Abstract: The disclosure relates to semiconductor structures and, more particularly, to structures for preventing dicing damage on photonics wafers. The structure includes: an optical waveguide structure to optical fiber interface formed on an integrated circuit; and a groove formed in a substrate and which includes a structure preventing a fluid pressure of a dicing operation from damaging the substrate along the groove.

Abstract: A dual bond pad structure for a wafer with laser die attachment and methods of manufacture are disclosed. The method includes forming a bonding layer on a surface of a substrate. The method further includes forming solder bumps on the bonding layer. The method further includes patterning the bonding layer to form bonding pads some of which comprise the solder bumps thereon. The method further includes attaching a laser diode to selected bonding pads using solder connections formed on the laser diode. The method further includes attaching an interposer substrate to the solder bumps formed on the bonding pads.

Abstract: A dual bond pad structure for a wafer with laser die attachment and methods of manufacture are disclosed. The method includes forming a bonding layer on a surface of a substrate. The method further includes forming solder bumps on the bonding layer. The method further includes patterning the bonding layer to form bonding pads some of which comprise the solder bumps thereon. The method further includes attaching a laser diode to selected bonding pads using solder connections formed on the laser diode. The method further includes attaching an interposer substrate to the solder bumps formed on the bonding pads.

Abstract: A dual bond pad structure for a wafer with laser die attachment and methods of manufacture are disclosed. The method includes forming a bonding layer on a surface of a substrate. The method further includes forming solder bumps on the bonding layer. The method further includes patterning the bonding layer to form bonding pads some of which comprise the solder bumps thereon. The method further includes attaching a laser diode to selected bonding pads using solder connections formed on the laser diode. The method further includes attaching an interposer substrate to the solder bumps formed on the bonding pads.