Abstract: Methods of maintaining or improving blood-brain barrier integrity and increasing resistance to cytokine-induced cell permeability are disclosed. It has been discovered that down-regulating the expression or production of sulfoglucuronyl glycolipids, for example SGPG, in endothelial cells of the blood-brain barrier or the blood-nerve barrier reduces apoptosis of these endothelial cells and thereby promotes the integrity of the barriers. Promoting the integrity of these barriers includes, but is not limited to reducing or inhibiting passage of immune cells, pathogenic immunoglobins, or bio-degrading molecules across the blood-brain barrier or blood-nerve barrier into the nervous system. Down-regulating expression or production or SGPG also increases the resistance of the endothelial cells to cytokine-induced cell permeability.

Abstract: The present invention is intended to find a novel function of a component in pre-germinated brown rice and to provide a safe and effective agent or functional food for prevention or improvement of a neuropathy or diabetic neuropathy The present invention provides an agent or functional food for prevention or improvement of a neuropathy or diabetic neuropathy including a total lipid fraction of pre-germinated brown rice as an effective ingredient.

Abstract: A multiplication accumulation circuit (abbreviated as “MAC”) has five input buses that carry signals for operands A, B, C, D and E, a control bus that carries signals for controlling the operations performed on the received operands, and an output bus that carries a signal generated by the MAC. Each of operands A, B, C and D can be four different operands that are used as follows by the MAC: (1) to perform two multiplications simultaneously, and (2) to perform an addition of the products of the two multiplications and the fifth operand E, e.g. generate on the output bus a signal of value A*C+B*D+E. Alternatively, operands A and B can be, respectively, the upper and lower halves of a first double word to be used as a multiplicand. Similarly, operands C and D can be the upper and lower halves of a second double word to be used as a multiplier.

Abstract: The present invention concerns mouse brain sialidase gene activity. The invention further relates to nucleic acids encoding sialidase protein, vectors containing and capable of expressing such nucleic acid, and recombinant host cells transformed with such nucleic acid. The invention also provides an amino acid sequence encoding an enzymatically active sialidase that is active in eukaryotic cells. The invention also provides host cells transfected or transformed with recombinant vectors expressing the sialidase gene from mouse brain in the host cells.

Abstract: The present invention provides methods for treating disease conditions associated with abnormal cellular proliferation, inflammation and viral infection or proliferation by the administration of ceramic analogs. The ceramic analogs appear to be specific for modulation of the enzyme PKC&zgr;.

Abstract: The present invention relates to isolated sialyltransferases, such as human or mouse GM3 synthase, human or mouse 4ST3GalVI, or human 7STGalNAcV sialyltransferase polypeptide, biologically-active polypeptide fragments thereof, and nucleic acids which code for it. This polypeptide has various activities including sialyltransferase activity. The invention relates to all aspects of sialyltransferase, or homologs thereof, including assays for modulators, activators, ligands, etc. The invention also relates to sialyltransferases expressed in cells and methods of using such cells to engineer specific sugar chains.

Abstract: A Viterbi calculator performs additions in parallel with comparison to compute the result of a single Viterbi equation in a single clock cycle. Therefore, the results of a butterfly operation involving two Viterbi equations can be computed in a single clock cycle by use of two Viterbi calculators. Alternatively, the butterfly operation can be implemented by a single Viterbi calculator used in a pipelined manner, although the throughput is at the rate of every two clock cycles. When a single Viterbi calculator is used in the pipelined manner, two multiplexers are used to alternately swap the constant values being supplied to the Viterbi calculator. The pipelined use of a single Viterbi calculator requires less space on an integrated circuit die than the parallel use of two Viterbi calculators, and is useful in applications where the variable data is available every two clock cycles (e.g. due to latency in accessing memory).

Abstract: Quotient digit selection logic is modified so as to prevent a partial remainder equal to the negative divisor from occurring. An enhanced quotient digit selection function prevents the working partial remainder from becoming negative if the result is exact, choosing a quotient digit of zero instead of a quotient digit of one when the actual partial remainder is zero. Using a five bit estimated partial remainder where the upper four bits are zero, a possible carry propagation into fourth most significant bit is detected. This can be accomplished by looking at the fifth most significant sum and carry bits of the redundant partial remainder. If they are both zero, then a carry propagation out of that bit position into the least significant position of the estimated partial remainder is not possible, and a quotient digit of zero is chosen. This provides a one cycle savings since negative partial remainders no longer need to be restored before calculating the sticky bit.

Abstract: A floating point multiplier with partial support for subnormal operands and results uses radix-4 or modified Booth encoding and a binary tree of 4:2 compressors to generate the 53.times.53 double-precision product. Delay matching techniques in the binary tree stage and in the final addition stage reduce cycle time. Improved rounding and sticky-bit generating techniques further reduce area and timing. The overall multiplier has a latency of 3 cycles, a throughput of 1 cycle, and a cycle time of 6.0 ns.

Abstract: A floating point mantissa final addition and rounding unit uses a conditional sum adder to reduce a redundant carry-save format 106-bit mantissa to a non-redundant properly rounded 53-bit double-precision mantissa. The conditional sum adder simultaneously speculatively computes both the sum and the incremented sum of the upper 52 bits of the carry-save portions. A rounding unit speculatively computes the lower one bit and two bits of the mantissa for the cases of mantissa overflow or non-overflow, respectively. The rounding unit produces an overflow carry signal and a non-overflow carry signal. A multiplexor selects the proper 53 mantissa output bits from among the two conditional sum adder outputs and the rounding unit mantissa outputs depending upon the most significant bits of the two conditional sum adder outputs and the overflow and non-overflow carry signals.

Abstract: The same hardware is used to implement calculations of the exponents for multiplication, division, and square root in either double or single precision. A multiplexor selects the appropriate bias value necessary for exponent computation for the given instruction type, operand precision, and output precision. A first operand multiplexor selects either the exponent of the first operand in the case of a multiplication or division instruction, and selects zero in the case of a square root instruction, since the square root operation only requires one operand. The second operand multiplexor selects the second exponent in the case of a multiplication instruction, the one's complement of the second exponent in the case of a division instruction, and the second exponent divided by two during a square root operation. Flip-flop registers latch the exponent and incremented exponent when a division or square root operation is pending.

Abstract: A method for fully supporting floating point multiplication using a combination of partial hardware support and partial software support traps to software when a subnormal operand is encountered and gross underflow cannot be determined without determining the leading zeros in the subnormal mantissa. A simplified hardware multiplier does not require leading zero detection or left or right shifting. The partial hardware support circuit allows single and double precision operands. The hardware multiplier unit only partially supports subnormal operands. If one of the operands is subnormal, the hardware multiplier unit will output zero and a gross underflow signal if the multiplication would result in gross underflow. There is a small minority of operand permutations that are not supported in hardware and thus require a greater time to compute by resorting to software. However, the vast majority of operand permutations gain reduced latency.