Patents by Inventor Robert Kaplar

Robert Kaplar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12218497
    Abstract: A disclosed switching apparatus, such as a circuit breaker, includes a transistor switch circuit connected between a power input terminal and a load terminal, and, connected to the power input terminal and bypassing the transistor switch circuit, a switchable bypass leg that is optically switched by a series-connected photoconductive semiconductor switch (PCSS). The transistor switch circuit includes at least one cascade of three or more series-connected transistors, and at least one resistor network configured to divide a voltage from a voltage source across a cascade of series-connected transistors. Operating the switch apparatus includes detecting whether a sensed electric current is in a fault condition, opening the transistor switch circuit upon detecting a fault condition, and then closing the PCSS so that the electric current is diverted onto a switchable bypass path. The opening of the transistor switch circuit comprises turning OFF a normally-ON transistor switch circuit.
    Type: Grant
    Filed: October 12, 2022
    Date of Patent: February 4, 2025
    Assignees: National Technology & Engineering Solutions of Sandia, LLC, UNM Rainforest Innovations
    Inventors: Gregory Pickrell, Jason Christopher Neely, Lee Gill, Jacob Mueller, Luciano Andres Garcia Rodriguez, Jack David Flicker, Emily Ann Schrock, Robert Kaplar, Harold P. Hjalmarson, Jane Lehr
  • Patent number: 11227844
    Abstract: A GaN diode EMP arrestor exhibits breakdown in <10 ns at reverse-bias voltage >20 kV. Additionally, the arrestor exhibits avalanche ruggedness at 1 kA/cm2 in a 1 mm2 device (i.e. 10 A absolute current) over a period of 500 ns following the onset of breakdown. Finally, the specific on-resistance in the forward direction is <20 m? cm2.
    Type: Grant
    Filed: October 1, 2019
    Date of Patent: January 18, 2022
    Assignee: National Technology & Engineering Solutions of Sandia, LLC
    Inventors: Robert Kaplar, Jack David Flicker, Olga Lavrova
  • Patent number: 10886841
    Abstract: A hybrid switched capacitor power converter for high-power applications is provided. The converter has a transistor-switched input-stage boost converter followed by a capacitor-and-diode ladder circuit. The converter is adapted to produce an output voltage of at least 5 kV at a power level of at least 0.5 kW. The ladder circuit includes one or more multi-stage rails.
    Type: Grant
    Filed: April 15, 2019
    Date of Patent: January 5, 2021
    Assignee: National Technology & Engineering Solutions of Sandia, LLC
    Inventors: Robert W. Brocato, Jason C. Neely, Lee Joshua Rashkin, Jarod James Delhotal, Jack David Flicker, Robert Kaplar, Joshua Stewart, James Richards
  • Patent number: 10553697
    Abstract: Methods are provided for fabricating a HEMT (high-electron-mobility transistor) that involve sequential epitaxial growth of III-nitride channel and barrier layers, followed by epitaxial regrowth of further III-nitride material through a window in a mask layer. The regrowth takes place on the barrier layer, only in the access region or regions. Devices made according to the disclosed methods are also provided.
    Type: Grant
    Filed: April 16, 2019
    Date of Patent: February 4, 2020
    Assignee: National Technology & Engineering Solutions of Sandia, LLC
    Inventors: Andrew Armstrong, Albert G. Baca, Andrew A. Allerman, Carlos Anthony Sanchez, Erica Ann Douglas, Robert Kaplar
  • Patent number: 10388753
    Abstract: Methods are provided for fabricating a HEMT (high-electron-mobility transistor) that involve sequential epitaxial growth of III-nitride channel and barrier layers, followed by epitaxial regrowth of further III-nitride material through a window in a mask layer. In examples, the regrowth takes place over exposed portions of the channel layer in the source and drain regions of the device, and the regrown material has a composition different from the barrier layer. In other examples, the regrowth takes place on the barrier layer, only in the access region or regions. Devices made according to the disclosed methods are also provided.
    Type: Grant
    Filed: March 14, 2018
    Date of Patent: August 20, 2019
    Assignee: National Technology & Engineering Solutions of Sandia, LLC
    Inventors: Andrew Armstrong, Albert G. Baca, Andrew A. Allerman, Carlos Anthony Sanchez, Erica Ann Douglas, Robert Kaplar
  • Patent number: 9917149
    Abstract: A diode includes a second semiconductor layer over a first semiconductor layer. The diode further includes a third semiconductor layer over the second semiconductor layer, where the third semiconductor layer includes a first semiconductor element over the second semiconductor layer. The third semiconductor layer additionally includes a second semiconductor element over the second semiconductor layer, wherein the second semiconductor element surrounds the first semiconductor element. Further, the third semiconductor layer includes a third semiconductor element over the second semiconductor element. Furthermore, a hole concentration of the second semiconductor element is less than a hole concentration of the first semiconductor element.
    Type: Grant
    Filed: May 27, 2016
    Date of Patent: March 13, 2018
    Assignee: National Technology & Engineering Solutions of Sandia, LLC
    Inventors: Jeramy Ray Dickerson, Jonathan Wierer, Jr., Robert Kaplar, Andrew A. Allerman
  • Patent number: 9761675
    Abstract: The present disclosure relates to resistive field structures that provide improved electric field profiles when used with a semiconductor device. In particular, the resistive field structures provide a uniform electric field profile, thereby enhancing breakdown voltage and improving reliability. In example, the structure is a field cage that is configured to be resistive, in which the potential changes significantly over the distance of the cage. In another example, the structure is a resistive field plate. Using these resistive field structures, the characteristics of the electric field profile can be independently modulated from the physical parameters of the semiconductor device. Additional methods and architectures are described herein.
    Type: Grant
    Filed: January 6, 2016
    Date of Patent: September 12, 2017
    Assignee: National Technology & Engineering Solutions of Sandia, LLC
    Inventors: Matthew Marinella, Sandeepan DasGupta, Robert Kaplar, Albert G. Baca