Patents by Inventor Robert Karmazin

Robert Karmazin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Automated layout for integrated circuits with nonstandard cells
    Patent number: 9852253
    Abstract: Methods, systems, and devices are disclosed for automatically generating physical layouts of integrated circuits. A circuit is partitioned into one or more cells based on a circuit description. The method further checks availability of a layout of a cell for all the cells generated during the partition step. If a layout of a cell is not available, the method generates a layout of the cell by an automatic tool, and packages the generated layout in a form of a standard cell compatible with a standard cell placement and routing tool. Afterwards, the generated layout may be exported to the standard cell placement and routing tool. Finally, the standard cell placement and routing tool may merge individual layouts of the one or more cells of the circuit to generate a layout for the circuit.
    Type: Grant
    Filed: May 19, 2014
    Date of Patent: December 26, 2017
    Assignee: Cornell University
    Inventors: Rajit Manohar, Robert Karmazin, Carlos Tadeo Ortega Otero
  • AUTOMATED LAYOUT FOR INTEGRATED CIRCUITS WITH NONSTANDARD CELLS
    Publication number: 20160085898
    Abstract: Methods, systems, and devices are disclosed for automatically generating physical layouts of integrated circuits. A circuit is partitioned into one or more cells based on a circuit description. The method further checks availability of a layout of a cell for all the cells generated during the partition step. If a layout of a cell is not available, the method generates a layout of the cell by an automatic tool, and packages the generated layout in a form of a standard cell compatible with a standard cell placement and routing tool. Afterwards, the generated layout may be exported to the standard cell placement and routing tool. Finally, the standard cell placement and routing tool may merge individual layouts of the one or more cells of the circuit to generate a layout for the circuit.
    Type: Application
    Filed: May 19, 2014
    Publication date: March 24, 2016
    Inventors: Rajit Manohar, Robert Karmazin, Carlos Tadeo Ortega Otero