Abstract: Techniques are disclosed relating to channel stalls or deactivations based on the latency of prior operations. In some embodiments, a processor includes a plurality of channel pipelines for a plurality of channels and a plurality of execution pipelines shared by the channel pipelines and configured to perform different types of operations provided by the channel pipelines. First scheduler circuitry may assign threads to channels and second scheduler circuitry may assign an operation from a given channel to a given execution pipeline based on decode of an operation for that channel. Dependency circuitry may, for a first operation that depends on a prior operation that uses one of the execution pipelines, determine, based on status information for the prior operation from the one of the execution pipelines, whether to stall the first operation or to deactivate a thread that includes the first operation from its assigned channel.

Abstract: Techniques are disclosed relating to channel stalls or deactivations based on the latency of prior operations. In some embodiments, a processor includes a plurality of channel pipelines for a plurality of channels and a plurality of execution pipelines shared by the channel pipelines and configured to perform different types of operations provided by the channel pipelines. First scheduler circuitry may assign threads to channels and second scheduler circuitry may assign an operation from a given channel to a given execution pipeline based on decode of an operation for that channel. Dependency circuitry may, for a first operation that depends on a prior operation that uses one of the execution pipelines, determine, based on status information for the prior operation from the one of the execution pipelines, whether to stall the first operation or to deactivate a thread that includes the first operation from its assigned channel.

Abstract: A circuit arrangement includes a preprocessing circuit configured to obtain context information related to a user location, a learning circuit configured to determine a predicted user movement based on context information related to a user location to obtain a predicted route and to determine predicted radio conditions along the predicted route, and a decision circuit configured to, based on the predicted radio conditions, identify one or more first areas expected to have a first type of radio conditions and one or more second areas expected to have a second type of radio conditions different from the first type of radio conditions and to control radio activity while traveling on the predicted route according to the one or more first areas and the one or more second areas.

Abstract: Techniques are disclosed relating to a hardware-supported flexible data structure for graphics processing. In some embodiments, dimensions of the data structure are configurable in an X direction, a Y direction, a number of samples per pixel, and an amount of data per sample. In some embodiments, these attributes are configurable using hardware registers. In some embodiments, the data structure is persistent across a tile being processed such that local memory context is accessible to both rendering threads of a render pass and mid-render compute threads.

Abstract: Techniques are disclosed relating to a hardware-supported flexible data structure for graphics processing. In some embodiments, dimensions of the data structure are configurable in an X direction, a Y direction, a number of samples per pixel, and an amount of data per sample. In some embodiments, these attributes are configurable using hardware registers. In some embodiments, the data structure is persistent across a tile being processed such that local memory context is accessible to both rendering threads of a render pass and mid-render compute threads.

Abstract: Embodiments of a unified shading controller are disclosed. The embodiments may provide a first functional unit configured to send a write request to a second functional unit. The write request may include data and the data may include one or more control bits. Upon receiving the write request, the second functional unit may check the one or more control bits, and hold the data in a given queue dependent upon the control bits.

Abstract: Embodiments of a unified shading controller are disclosed. The embodiments may provide a first functional unit configured to send a write request to a second functional unit. The write request may include data and the data may include one or more control bits. Upon receiving the write request, the second functional unit may check the one or more control bits, and hold the data in a given queue dependent upon the control bits.

Abstract: Described are a secure obfuscation network (SON) and ingress nodes, transit nodes and egress nodes used in such a network. Also described is a method for implementing such a network.

Abstract: A circuit for implementing latch array functions on an integrated circuit. Portions of the logic devices included in the implementation of the latch array functions that are controlled by a common signal, may be arranged in a particular alignment. A single layer uni-directionally conductive material may connect the common signal to the logic devices.

Abstract: A circuit for implementing latch array functions on an integrated circuit. Portions of the logic devices included in the implementation of the latch array functions that are controlled by a common signal, may be arranged in a particular alignment. A single layer uni-directionally conductive material may connect the common signal to the logic devices.

Abstract: A computer implemented method, data processing system, and computer usable code are provided for testing multi-core microprocessors. A test process initiates testing on communication bus interfaces associated with a set of processor cores on the multiprocessor in which the communication bus interfaces are disabled and wherein the testing uses a set of isolation test sequences to obtain results. The process identifies a set of functional processor cores in the set of processor cores based upon the results. The process also initiates a ramp logic built-in self-test to test a ramp associated with a functional processor core in the set of functional processor cores, wherein the ramp logic built-in self-test determines if the communication bus interface associated with functional processor core in the set of functional processor cores is functional.

Abstract: A multi-operand decimal adder is described that performs addition on multiple binary coded decimal (BCD) operands. The multi-operand decimal adder uses binary carry-save adders to produce intermediate sums and carries, and outputs a decimal result based on the intermediate sums and carries. In various configurations, the multi-operand decimal adder may perform speculative or non-speculative binary carry-save addition. The multioperand decimal adders achieve a reasonable critical path. As a result, the decimal adders and the techniques described herein may be especially suited for numerically intensive commercial applications, such as spreadsheet or financial applications where large amounts of decimal data typically need to be processed quickly.