Abstract: A method and apparatus to control execution of nested loops is disclosed. The method and apparatus stores the loop level of a current loop in execution and uses this loop level to manage a data set provided for each loop. The data set for each loop includes a start address, an end address, and a loop counter or a loop flag, respectively. The method and apparatus allows arbitrary nested loops to be controlled without increasing a complexity level of the circuit and allows additional loop control. The only precondition is that the loop end addresses are different.

Abstract: In some embodiments a flexible scalable Boolean processing apparatus is disclosed. The apparatus can include a register to accept Boolean inputs, a Boolean lookup table coupled to the register to accept the Boolean inputs and to perform a Boolean function on the Boolean inputs and to produce a result. The apparatus can also include a multiplexer to select an executable instruction to process the result in response to an instruction select signal. In some embodiments the apparatus can include a shifter module to shift the result to a predetermined bit location in a register and a filler module to fill the register if a result has fewer bits than a number of bits required to fill the register. Other embodiments are also disclosed.

Abstract: Methods and apparatuses that can determining a median value from a set of m values are disclosed. The method can include receiving a set of values, separating the set of values into subsets where some subsets have multiple values and at least one other has a single value. The subsets having multiple variables can be sorted based on the magnitudes of the multiple values. The values from the subset can be processed to find sub-median values, and a median value can be determined from the set of values utilizing the sub-median values and sorted values. Other embodiments are also disclosed.

Abstract: Methods and processor architectures for the execution of instruction having a condition are disclosed. Very long instruction words can be loaded from a memory unit into an instruction word decoder and the decoder can separate the VLIW into processable sequences. Each processable sequence can be processable by a processing unit among a plurality of processing units. Each processable sequence can be executed independently in the absence of a condition in the processable sequences, and when the processable sequences contain a condition, processing units can be logically coupled together to add processing resources to a processing intensive condition type code to assist in disposing of the conditional execution quickly by assigning these additional resources.