Abstract: An apparatus for decoding binary data from one form to another has a register adapted to receive the input bit signals. A plurality of data paths are connected to the register, with a delay means in at least one of the paths. Decoding means is adapted to generate output bit signals in response to the input bit signals. Logic means determines the correct phase relationship between the input bit signals and the output bit signals. Switching means, responsive to the logic means, selects the data path from the register to produce the correct phase relationship between the input bit signals and the output bit signals.

Abstract: A system which employs a parallel to serial converter and a serial shift register encoder for encoding a multibyte sync pattern in a fixed rate variable word length run-length limited code wherein less than a single character of data is supplied to the encoder from the parallel to serial converter to encode the multibyte sync pattern. The system provides for feeding a first portion of the encoded sync pattern back to the encoder through a serial decoder which provides a serial bit stream that is identical to the initial pattern provided to the encoder. Suitable control circuitry is employed to control the phasing of the end of the initial bit stream and the beginning of the decoded bit stream fed back to the encoder. Once the feedback path is established, the total length of the encoded sync pattern is independent of the single character initially supplied to the encoder.