Patents by Inventor Robert L. Bristol

Robert L. Bristol has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10957844
    Abstract: Magneto-electric spin orbital (MESO) structures having functional oxide vias, and method of fabricating magneto-electric spin orbital (MESO) structures having functional oxide vias, are described. In an example, a magneto-electric spin orbital (MESO) device includes a source region and a drain region in or above a substrate. A first via contact is on the source region. A second via contact is on the drain region, the second via contact laterally adjacent to the first via contact. A plurality of alternating ferromagnetic material lines and non-ferromagnetic conductive lines is above the first and second via contacts. A first of the ferromagnetic material lines is on the first via contact, and a second of the ferromagnetic material lines is on the second via contact. A spin orbit coupling (SOC) via is on the first of the ferromagnetic material lines. A functional oxide via is on the second of the ferromagnetic material lines.
    Type: Grant
    Filed: December 23, 2016
    Date of Patent: March 23, 2021
    Assignee: Intel Corporation
    Inventors: Jasmeet S. Chawla, Sasikanth Manipatruni, Robert L. Bristol, Chia-Ching Lin, Dmitri E. Nikonov, Ian A. Young
  • Publication number: 20210082800
    Abstract: Advanced lithography techniques including sub-10 nm pitch patterning and structures resulting therefrom are described. Self-assembled devices and their methods of fabrication are described.
    Type: Application
    Filed: December 2, 2020
    Publication date: March 18, 2021
    Inventors: Richard E. SCHENKER, Robert L. BRISTOL, Kevin L. LIN, Florian GSTREIN, James M. BLACKWELL, Marie KRYSAK, Manish CHANDHOK, Paul A. NYHUS, Charles H. WALLACE, Curtis W. WARD, Swaminathan SIVAKUMAR, Elliot N. TAN
  • Publication number: 20210050261
    Abstract: Subtractive plug and tab patterning with photobuckets for back end of line (BEOL) spacer-based interconnects is described. In an example, a back end of line (BEOL) metallization layer for a semiconductor structure includes an inter-layer dielectric (ILD) layer disposed above a substrate. A plurality of conductive lines is disposed in the ILD layer along a first direction. A conductive tab is disposed in the ILD layer, the conductive tab coupling two of the plurality of conductive lines along a second direction orthogonal to the first direction. A conductive via is coupled to one of the plurality of conductive lines, the conductive via having a via hardmask thereon. An uppermost surface of each of the ILD layer, the plurality of conductive lines, the conductive tab, and the via hardmask is planar with one another.
    Type: Application
    Filed: October 30, 2020
    Publication date: February 18, 2021
    Inventors: Kevin LIN, Robert L. BRISTOL, Richard E. SCHENKER
  • Patent number: 10892184
    Abstract: Approaches based on photobucket floor colors with selective grafting for semiconductor structure fabrication, and the resulting structures, are described. For example, a grating structure is formed above an ILD layer formed above a substrate, the grating structure including a plurality of dielectric spacers separated by alternating first trenches and second trenches, grafting a resist-inhibitor layer in the first trenches but not in the second trenches, forming photoresist in the first trenches and in the second trenches, exposing and removing the photoresist in select ones of the second trenches to a lithographic exposure to define a set of via locations, etching the set of via locations into the ILD layer, and forming a plurality of metal lines in the ILD layer, where select ones of the plurality of metal lines includes an underlying conductive via corresponding to the set of via locations.
    Type: Grant
    Filed: September 30, 2016
    Date of Patent: January 12, 2021
    Assignee: Intel Corporation
    Inventors: Robert L. Bristol, Kevin L. Lin, James M. Blackwell, Rami Hourani, Eungnak Han
  • Patent number: 10892223
    Abstract: Advanced lithography techniques including sub-10 nm pitch patterning and structures resulting therefrom are described. Self-assembled devices and their methods of fabrication are described.
    Type: Grant
    Filed: December 23, 2016
    Date of Patent: January 12, 2021
    Assignee: Intel Corporation
    Inventors: Richard E. Schenker, Robert L. Bristol, Kevin L. Lin, Florian Gstrein, James M. Blackwell, Marie Krysak, Manish Chandhok, Paul A. Nyhus, Charles H. Wallace, Curtis W. Ward, Swaminathan Sivakumar, Elliot N. Tan
  • Publication number: 20210005511
    Abstract: Damascene plug and tab patterning with photobuckets for back end of line (BEOL) spacer-based interconnects is described. In an example, a back end of line (BEOL) metallization layer for a semiconductor structure includes an inter-layer dielectric (ILD) layer disposed above a substrate. A plurality of conductive lines is disposed in the ILD layer along a first direction. A conductive tab is disposed in the ILD layer. The conductive tab couples two of the plurality of conductive lines along a second direction orthogonal to the first direction.
    Type: Application
    Filed: September 18, 2020
    Publication date: January 7, 2021
    Inventors: Kevin LIN, Robert L. BRISTOL, Richard E. SCHENKER
  • Patent number: 10867853
    Abstract: Subtractive plug and tab patterning with photobuckets for back end of line (BEOL) spacer-based interconnects is described. In an example, a back end of line (BEOL) metallization layer for a semiconductor structure includes an inter-layer dielectric (ILD) layer disposed above a substrate. A plurality of conductive lines is disposed in the ILD layer along a first direction. A conductive tab is disposed in the ILD layer, the conductive tab coupling two of the plurality of conductive lines along a second direction orthogonal to the first direction. A conductive via is coupled to one of the plurality of conductive lines, the conductive via having a via hardmask thereon. An uppermost surface of each of the ILD layer, the plurality of conductive lines, the conductive tab, and the via hardmask is planar with one another.
    Type: Grant
    Filed: May 27, 2016
    Date of Patent: December 15, 2020
    Assignee: Intel Corporation
    Inventors: Kevin Lin, Robert L. Bristol, Richard E. Schenker
  • Patent number: 10804141
    Abstract: Damascene plug and tab patterning with photobuckets for back end of line (BEOL) spacer-based interconnects is described. In an example, a back end of line (BEOL) metallization layer for a semiconductor structure includes an inter-layer dielectric (ILD) layer disposed above a substrate. A plurality of conductive lines is disposed in the ILD layer along a first direction. A conductive tab is disposed in the ILD layer. The conductive tab couples two of the plurality of conductive lines along a second direction orthogonal to the first direction.
    Type: Grant
    Filed: May 27, 2016
    Date of Patent: October 13, 2020
    Assignee: Intel Corporation
    Inventors: Kevin Lin, Robert L. Bristol, Richard E. Schenker
  • Patent number: 10796909
    Abstract: Surface-aligned lithographic patterning approaches for back end of line (BEOL) interconnect fabrication, and the resulting structures, are described. In an example, an integrated circuit structure includes a substrate. A plurality of alternating first and second conductive lines is along a first direction of a back end of line (BEOL) metallization layer in a first inter-layer dielectric (ILD) layer above the substrate. A conductive via is on and electrically coupled to one of the conductive lines of the plurality of alternating first and second conductive lines, the conductive via centered over the one of the conductive lines. A second ILD layer is above plurality of alternating first and second conductive lines and laterally adjacent to the conductive via. The second ILD layer has an uppermost surface substantially co-planar with the flat top surface of the conductive via.
    Type: Grant
    Filed: December 2, 2016
    Date of Patent: October 6, 2020
    Assignee: Intel Corporation
    Inventors: Robert L. Bristol, Kevin L. Lin, James M. Blackwell
  • Publication number: 20200279805
    Abstract: Techniques are disclosed for forming vias for integrated circuit structures. During an additive via formation process, a dielectric material is deposited, an etch stop layer is deposited, a checkerboard pattern is deposited on the etch stop layer, regions in the checkerboard pattern are removed where it is desired to have vias, openings are etched in the dielectric material through the removed regions, and the openings are filled with a first via material. This is then repeated for a second via material. During the subtractive via formation process, a first via material is deposited, an etch stop layer is deposited, a checkerboard pattern is deposited on the etch stop layer, regions in the checkerboard pattern are removed where it is not desired to have vias, openings are etched in the first via material through the removed regions. This is then repeated for a second via material.
    Type: Application
    Filed: November 3, 2017
    Publication date: September 3, 2020
    Applicant: INTEL CORPORATION
    Inventors: Sasikanth Manipatruni, Jasmeet S. Chawla, Chia-Ching Lin, Dmitri E. Nikonov, Ian A. Young, Robert L. Bristol
  • Patent number: 10644113
    Abstract: Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a quantum well stack including a quantum well layer; and a plurality of gates disposed above the quantum well stack, wherein individual ones of the plurality of gates have a footprint shape with two opposing linear faces and two opposing curved faces.
    Type: Grant
    Filed: August 10, 2016
    Date of Patent: May 5, 2020
    Assignee: Intel Corporation
    Inventors: James S. Clarke, Robert L. Bristol, Ravi Pillarisetty, Jeanette M. Roberts, Hubert C. George, Nicole K. Thomas
  • Patent number: 10615117
    Abstract: There is disclosed in an example an integrated circuit, including: a first layer having a dielectric, a first conductive interconnect and a second conductive interconnect; a second layer having a third conductive interconnect; a conductive via between the first layer and the second layer to electrically couple the second conductive interconnect to the third conductive interconnect; a dielectric plug disposed vertically between the first layer and second layer and disposed to prevent the via from electrically shorting to the first conductive interconnect; and a dielectric cap covering the dielectric plug.
    Type: Grant
    Filed: December 29, 2016
    Date of Patent: April 7, 2020
    Assignee: Intel Corporation
    Inventors: Kevin L. Lin, Robert L. Bristol, Rami Hourani, James M. Blackwell
  • Publication number: 20200066521
    Abstract: A computing device including tight pitch features and a method of fabricating a computing device using colored spacer formation is disclosed. The computing device includes a memory and an integrated circuit coupled to the memory. The integrated circuit includes a first multitude of features above a substrate. The integrated circuit die includes a second multitude of features above the substrate. The first multitude of features and the second multitude of features are same features disposed in a first direction. The first multitude of features interleave with the second multitude of features. The first multitude of features has a first size and the second multitude of features has a second size.
    Type: Application
    Filed: March 31, 2017
    Publication date: February 27, 2020
    Inventors: Kevin LIN, Rami HOURANI, Elliot N. TAN, Manish CHANDHOK, Anant H. JAHAGIRDAR, Robert L. BRISTOL, Richard E. SCHENKER, Aaron Douglas LILAK
  • Publication number: 20200066629
    Abstract: Advanced lithography techniques including sub-10 nm pitch patterning and structures resulting therefrom are described. Self-assembled devices and their methods of fabrication are described.
    Type: Application
    Filed: December 23, 2016
    Publication date: February 27, 2020
    Inventors: Richard E. SCHENKER, Robert L. BRISTOL, Kevin L. LIN, Florian GSTREIN, James M. BLACKWELL, Marie KRYSAK, Manish CHANDHOK, Paul A. NYHUS, Charles H. WALLACE, Curtis W. WARD, Swaminathan SIVAKUMAR, Elliot N. TAN
  • Patent number: 10553532
    Abstract: Embodiments of the invention include interconnect structures with overhead vias and through vias that are self-aligned with interconnect lines and methods of forming such structures. In an embodiment, an interconnect structure is formed in an interlayer dielectric (ILD). One or more first interconnect lines may be formed in the ILD. The interconnect structure may also include one or more second interconnect lines in the ILD that arranged in an alternating pattern with the first interconnect lines. Top surfaces of each of the first and second interconnect lines may be recessed below a top surface of the ILD. The interconnect structure may include a self-aligned overhead via formed over one or more of the first interconnect lines or over one or more of the second interconnect lines. In an embodiment, a top surface of the self-aligned overhead via is substantially coplanar with a top surface of the ILD.
    Type: Grant
    Filed: December 24, 2014
    Date of Patent: February 4, 2020
    Assignee: Intel Corporation
    Inventors: Richard E. Schenker, Manish Chandhok, Robert L. Bristol, Mauro J. Kobrinsky, Kevin Lin
  • Patent number: 10490416
    Abstract: Described herein are structures and methods for preparing photobuckets for lithography, e.g. photolithography or electron-beam lithography. One method includes arranging photobuckets on a material to be etched using lithography and providing a layer of a first material at least on inner side walls of the photobuckets, followed by filling the photobuckets with a second material. The second material is more lithosensitive than the first material and the first material could be not lithosensitive at all. Layering each photobucket from the inner side wall(s) of the photobucket towards the center of the photobucket with materials that are increasingly more lithosensitive results in an improved control of lithographic patterning by reducing or eliminating edge placement errors of accidentally exposing photobuckets that should not have been exposed.
    Type: Grant
    Filed: November 16, 2015
    Date of Patent: November 26, 2019
    Assignee: Intel Corporation
    Inventors: Robert L. Bristol, James M. Blackwell
  • Patent number: 10457548
    Abstract: A conductive layer is deposited into a trench in a sacrificial layer on a substrate. An etch stop layer is deposited over the conductive layer. The sacrificial layer is removed to form a gap. In one embodiment, a beam is over a substrate. An interconnect is on the beam. An etch stop layer is over the beam. A gap is between the beam and the etch stop layer.
    Type: Grant
    Filed: June 22, 2015
    Date of Patent: October 29, 2019
    Assignee: Intel Corporation
    Inventors: Kevin Lai Lin, Chytra Pawashe, Raseong Kim, Ian A. Young, Kanwal Jit Singh, Robert L. Bristol
  • Publication number: 20190318959
    Abstract: Approaches based on differential hardmasks for modulation of electrobucket sensitivity for semiconductor structure fabrication, and the resulting structures, are described. In an example, a method of fabricating an interconnect structure for an integrated circuit includes forming a hardmask layer above an inter-layer dielectric (ILD) layer formed above a substrate. A plurality of dielectric spacers is formed on the hardmask layer. The hardmask layer is patterned to form a plurality of first hardmask portions. A plurality of second hardmask portions is formed alternating with the first hardmask portions. A plurality of electrobuckets is formed on the alternating first and second hardmask portions and in openings between the plurality of dielectric spacers. Select ones of the plurality of electrobuckets are exposed to a lithographic exposure and removed to define a set of via locations.
    Type: Application
    Filed: December 23, 2016
    Publication date: October 17, 2019
    Inventors: Kevin L. LIN, Robert L. BRISTOL, James M. BLACKWELL, Rami HOURANI, Marie KRYSAK
  • Publication number: 20190318958
    Abstract: Approaches based on photobucket floor colors with selective grafting for semiconductor structure fabrication, and the resulting structures, are described. For example, a grating structure is formed above an ILD layer formed above a substrate, the grating structure including a plurality of dielectric spacers separated by alternating first trenches and second trenches, grafting a resist-inhibitor layer in the first trenches but not in the second trenches, forming photoresist in the first trenches and in the second trenches, exposing and removing the photoresist in select ones of the second trenches to a lithographic exposure to define a set of via locations, etching the set of via locations into the ILD layer, and forming a plurality of metal lines in the ILD layer, where select ones of the plurality of metal lines includes an underlying conductive via corresponding to the set of via locations.
    Type: Application
    Filed: September 30, 2016
    Publication date: October 17, 2019
    Inventors: Robert L. BRISTOL, Kevin L. LIN, James M. BLACKWELL, Rami HOURANI, Eungnak HAN
  • Publication number: 20190311984
    Abstract: There is disclosed in an example an integrated circuit, including: a first layer having a dielectric, a first conductive interconnect and a second conductive interconnect; a second layer having a third conductive interconnect; a conductive via between the first layer and the second layer to electrically couple the second conductive interconnect to the third conductive interconnect; a dielectric plug disposed vertically between the first layer and second layer and disposed to prevent the via from electrically shorting to the first conductive interconnect; and a dielectric cap covering the dielectric plug.
    Type: Application
    Filed: December 29, 2016
    Publication date: October 10, 2019
    Applicant: Intel Corporation
    Inventors: Kevin L. Lin, Robert L. Bristol, Rami Hourani, James M. Blackwell