Abstract: A receiver circuit uses switched capacitor circuits to couple signals received over a communication facility to connected apparatus. During a first time interval a capacitor is connected across each lead of a facility to sample the facility voltages. During a second time interval these capacitors are disconnected from the facility lines and reconnected in series as the input to a voltage regenerator circuit. The regenerator circuit reconstructs the received signals for output to connected apparatus.

Abstract: A receiver circuit uses a switched capacitor circuit to couple either analog or digital signals received over a two lead communication facility to connected apparatus. During a first time interval, a capacitor is connected across a lead of a facility to sample the facility voltage. During a second time interval, this capacitor is disconnected from that lead and reconnected in series between the second facility lead and the input to a voltage regenerator circuit. An appropriate regenerator circuit is selected to reconstruct either the received analog or digital signals for output to connected apparatus.

Abstract: Disclosed is a charge redistribution codec employing a two capacitor network for developing a progression of reference voltages having a binary relationship to each other for each analog input sample to be encoded. Linear encoding of input samples is achieved with the use of two such charge redistribution networks, with one developing positive reference voltages and the other developing negative reference voltages. Analog input samples are placed in an encoding capacitor and based on the polarity of the voltage across the capacitor either a positive or a negative charge is added iteratively to the capacitor in the direction of driving the voltage across that capacitor to zero. A code is developed by assigning at each iteration one value to an output code bit when a positive voltage is added and the opposite value to the bit when a negative voltage is added.

Abstract: An analog-to-digital converter circuit is disclosed employing a plurality of comparators each having the same reference voltage input. At each comparator stage plus and minus binary "bit weights" are developed. Selection of either the positive or negative bit weights at a stage allows a binary fraction to be added or subtracted. The number of comparator stages need only equal the number of desired digit positions in the output instead of having one comparator for each quantizing level. The comparator stages operate in a "wave" or "pipeline" manner under the control of a plurality of high speed wave forms so that each stage decodes its respective binary digit for one analog sample while the other stages are decoding their respective binary digits of other analog samples.

Abstract: A loop network is disclosed in which the ports have access to time slots on each of two buses. The buses carry the time slots in opposite directions. Ports are addressed by marking a bit of a time slot word on one bus and a bit of a time slot word on the other bus so that the two marked bits will arrive within a predetermined number of bit intervals of each other at the addressed port. Time slots are seized by an upstream port writing a predetermined pattern into an arriving idle time slot and by the downstream port recognizing the arrival of that predetermined pattern. A time slot may be reused during the remainder of its passage around the loop after it is rendered idle by the downstream port of a connection.

Abstract: The subject sampling filter employs fractional period displacement of samples to force additional nulls in the filter characteristic response. This sampling method and cascading antialiasing filters provides a filter structure which minimizes the complexity of the circuit yet which provides great flexibility to implement a desired filter characteristic.

Abstract: The disclosed four-wire to two-wire converter employs a pair of dual detector opto-isolator circuits to both linearize the converter transfer characteristic and eliminate signal feedback between ports. This is accomplished by feeding back the signals transmitted by the transmit portion of the four-wire port through the auxiliary detector of the opto-isolator circuit connected across the two-wire port to prevent signal feedback to the receive portion of the four-wire port. This opto-isolator feedback arrangement eliminates the need for complex feedback and impedance matching circuitry thereby enabling direct connection of the opto-isolator circuits to the communication paths while also rendering the converter circuit transparent to signals appearing thereon.

Abstract: A reversible analog to digital converter is designed for high precision in the interrelation of analog voltages and binary digital representations. An upper and a lower limit voltage converge on the analog voltage level in binarily decreasing steps. The upper and lower limits are averaged to form a trial voltage; in A/D conversion the trial voltage replaces one of the limits in accordance with a comparison between the analog voltage and the trial voltage, in digital to analog conversion the trial voltage replaces one of the limits in accordance with a binary input signal.

Abstract: The disclosed analog to digital converter employs a single signal propagation path thereby necessitating only one holding capacitor (101) per stage (STAGE 1) of coding. The first terminal (B) of each holding capacitor (101) is connected to a reference voltage (L1) such as a resistive divider (106, 116, 126, 136, 146, 150, 151, V.sub.HI) which has binary weighted taps (L1-L5). The other terminal (A) of each holding capacitor (101) is connected to the analog signal input (INPUT). The reference voltage (L1) and the analog sample (V1) are compared and, for a zero decision, the stored analog sample (V1) is directly passed on to the subsequent stage (STAGE 2) by a buffer circuit (102). For a one decision, the aforementioned first terminal (B) of the holding capacitor (101) is switched from the tap of the resistive divider to circuit ground thereby subtracting that binary weight (L1) from the signal (V1) stored on the holding capacitor (101).

Abstract: The disclosed signal multiplexing circuit (110) makes use of a single pair of wires (T, R) to interface a data and voice communication circuit such as an electronic key telephone (EKT) station set (100) with a central data and voice communication system such as a communication system (BCS). The signal multiplexing circuit transmits outgoing standard voice signals, outgoing auxiliary signals and outgoing data and, in turn, simultaneously receives incoming standard voice signals, incoming data and incoming auxiliary signals on the single pair of wires. Both time division and frequency separation techniques are concurrently employed to achieve multiple use of the single pair of wires without crosstalk between the plurality of signals. The data signals are transmitted as bipolar bit pairs preceded by a data start pulse pair. The outgoing data bipolar bit pairs are delayed until the center transition of the incoming data bipolar pulse pair is detected.

Abstract: Digital words defining magnitude levels of samples of phases of a wave cycle are stored in two memories arranged to store samples of 440 Hz and 480 Hz tones. The words are read out of the memories in a predetermined order which defines successive phases of the wave cycles, each word being read out a plurality of times before the next successive word is read to increase the sample rate without increasing the number of stored words. The words are converted to the defined levels to form step waves corresponding to the two tones and summed and the resultant composite wave is integrated to form a relatively smooth composite tone (ringback) signal.

Abstract: The disclosed signal multiplexing circuit (110) makes use of a single pair of wires (T, R) to interface a data and voice communication circuit such as an electronic key telephone (EKT) station set (100) with a central data and voice communication system such as a communication system (BCS). The signal multiplexing circuit transmits outgoing standard voice signals, outgoing auxiliary signals and outgoing data and, in turn, simultaneously receives incoming standard voice signals, incoming data and incoming auxiliary signals on the single pair of wires. Both time division and frequency separation techniques are concurrently employed to achieve multiple use of the single pair of wires without crosstalk between the plurality of signals. The data signals are transmitted as bipolar bit pairs preceded by a data start pulse pair. The outgoing data bipolar bit pairs are delayed until the center transition of the incoming data bipolar pulse pair is detected.