Abstract: A microprocessor system includes a core CPU for instruction execution and a coprocessor interconnected with said core CPU for system control and exception processing. The coprocessor includes a plurality of exception handling registers including an exception program counter having a restart location stored therein for use after an exception is serviced, a status register having operating mode identification and interrupt enabling bits, and a configuration and cache control register. Interrupt processing is compatible with a plurality of instruction sets with a particular instruction set being designated by setting at least one bit in the configuration and cache control register. Registers are provided to save the operating state of the CPU prior to interrupt enable, the operating state of the CPU being restored after exception processing is completed and user mode is reestablished.

Abstract: An add with circular mask operation is executed in a RISC processor which includes a coprocessor having a register for storing a circular mask value. A circular mask instruction to the coprocessor includes a value in an immediate field and identifies a general register (RS), and a destination register (RT). The coprocessor operates on the value stored in the general register with the value in the immediate field and then masks the results using the circular mask value. The results are then stored in the destination register. The operation includes sign-extending the immediate field before adding to the contents of the general register to provide a sum, and the sum is then masked with the circular mask value.

Abstract: A microprocessor core operating on instructions in a dual six-stage pipeline. Instructions are fetched and decoded by an instruction scheduling unit which includes a queuing stage for facilitating conditional branch operations. Instructions can be executed in five execution units including a load/store/add unit, an ALU unit, a shift/multiply unit, a branch unit, and a coprocessor which interfaces with the microprocessor core. Exceptions are handled by the coprocessor which includes a plurality of registers and a multiple entry translation lookaside buffer and an exception program counter. When an exception is detected the coprocessor loads the exception program counter with a restart address where execution can resume after the exception is serviced, the plurality of registers being used during the exception processing.

Abstract: A pipelined microprocessor is provided with a queuing stage between an instruction fetch stage and an instruction decode stage to facilitate branch instructions and to receive instructions from the fetch stage when the decode stage is stalled. If a branch is incorrectly anticipated the queuing stage has nonbranch sequential instructions for the decode stage while the fetch stage is restarted at the nonbranch sequential instruction stream.

Abstract: A microprocessor core operating on instructions in a dual six-stage pipeline. Instructions are fetched and decoded by an instruction scheduling unit which includes a queuing stage for facilitating conditional branch operations. Instructions can be executed in five execution units including a load/store/add unit, an ALU unit, a shift/multiply unit, a branch unit, and a coprocessor which interfaces with the microprocessor core. Exceptions are handled by the coprocessor which includes a plurality of registers and a multiple entry translation lookaside buffer and an exception program counter. When an exception is detected the coprocessor loads the exception program counter with a restart address where execution can resume after the exception is serviced, the plurality of registers being used during the exception processing.

Abstract: A high performance graphics applications controller having a core processor and a coprocessor to independently perform desired graphics functions is provided. The core processor and the coprocessor divides processing tasks to speed execution and to reduce the burden on the host CPU. A direct memory access (DMA) controller cooperates with the coprocessor to generate source and destination addresses and employs a unique set of commands to speed operation. The core processor employs a local CPU and data and address catches to locally perform desired graphics operations independently but in conjunction with the coprocessor. The present invention has particular application with smart terminals and wherever pixel oriented data is required.