Abstract: A voltage detection circuit has a first MOSFET device having a drain, a gate, and a source terminal. A feedback element is coupled to the drain terminal and the gate terminal of the first MOSFET device. An input voltage is coupled to the gate terminal of the first MOSFET device. The voltage detection circuit is actively detecting a voltage from when the input voltage is in an OFF-state voltage region of the first MOSFET device. This detection continues through when the input voltage is at a sub-threshold voltage region of the first MOSFET, to when the input voltage exceeds the threshold voltage of the first MOSFET. This voltage detection circuit dissipates only a pre-selected drain-current at a level exceeding the drain-leakage current of the first MOSFET, as power dissipation.

Abstract: An improved voltage reference circuit relies on electrically adjustable analog devices fabricated on a common substrate. The circuit has two electrically adjustable matched transistor pairs. A first matched transistor pair includes an adjusting transistor and a differential pair transistor. A second matched transistor pair also includes an adjusting transistor and a differential pair transistor. Each of the matched transistor pairs share an insulated gate or electrically connected insulated gates. Geometrical and electrical matching occurs as between the two adjusting transistors and between the two differential pair transistors. The two differential pair transistors are electrically connected at the source terminals to form a differential circuit. A feedback loop, which includes an amplifier, a fixed resistor and a current source complete the circuit.

Abstract: An improved integrated electrically adjustable analog transistor device is delineated wherein the device has multiple sub-structures to optimize performance of the device. One of the sub-structures is particularly well suited for charging the device's insulated gate. Additional sub-structures, each different in dimensions and electrical characteristics from the first sub-structure, are implemented for optimal use with an external electrical circuit.

Abstract: An integrated operational amplifier device has an operational amplifier device, and means connected to the operational amplifier device for providing at least one of a positive and a negative electrically adjustable input offset voltages. The system further comprises semiconductor device means for affecting the amount of input offset voltage supplied to the operational amplifier device. The system further comprises charge storage device means for storing a charge for maintaining a constant input offset voltage for controlling the operation of the semiconductor device means. The charge storage device means, the semiconductor device means, and the operational amplifier device are a monolithic integrated circuit.

Abstract: A transducer for generating an amplified signal in response to a stimulus. The transducer includes a sensing structure for sensing a stimulus and for generating a signal functionally related to the stimulus. An amplifier circuit, utilizing a single amplifier, amplifies the signal by a predetermined gain. Resistive elements in the amplified circuit are formed on the same substrate as the sensing structure and define the predetermined gain of the amplifier circuit. The transducer generates a signal having zero magnitude in response to zero pressure on the sensing structure and has fewer than seven resistors requiring laser trimming.

Abstract: An analog MOS transistor device allows the user to set the threshold characteristics of the device. This transistor device is fabricated using conventional CMOS fabrication materials and methods. An insulated gate spans across a source junction, a drain junction, and a control junction. This gate can be charged or discharged to a desired voltage level by injecting or removing charge at the insulated gate. The insulated gate has no conductor connection, and is only capacitively coupled to the source junction, drain junction and control junction. The user sets the voltage on the insulated gate, then varies the voltage impressed on the control junction as the application requires. The user can set the channel conductivity characteristics of the device by setting the charge level on the insulated gate, and by varying the voltage on the control junction, both of which may be dynamically adjusted in-circuit.

Abstract: Integrated MOS devices with intermediate ion-implanted regions for minimizing device interaction. Several configurations are detailed; they are individually or, in combination, extremely useful in maximizing the density of ROM functions implemented in the integrated circuit format. In particular, one of the embodiments enhances the achievable density in a row-column array used in ROM memories. Used together, the embodiments are especially suited for a ROM of the CMOS genre.

Abstract: This is an improved approach to the operation of an integrated circuit memory, especially of the MOS type. The approach is especially suitable for use with CMOS read-only memories (ROMs). Specific improvements include address-triggered pulse generation, power switching and sharing for individual cells, a pseudo-dynamic approach to achieve quasi-static operation, self-compensating means for both "word" lines and "bit" lines, use of complementary decoding devices for the mutually orthogonal directions in the memory, and an improved output function. Specific circuitry for implementing the above approaches in a CMOS integrated circuit includes an address-triggered pulse generator, a self-tracking reference voltage source derived from both the "word" lines and the "bit" lines, an output stage with a CMOS driver into a bipolar transistor, and a sense amplifier including a capacitor.

Abstract: Improved circuitry for providing a stable reference voltage in complementary transistor circuitry. The circuitry comprises a pair of complementary transistors and a pair of zener diodes interconnected to reduce reference voltage variation with respect to supply voltages.

Abstract: A detection circuit particularly adapted as a smoke detector employs a minimum number of components by a CMOS integrated circuit which receives directly the output of a smoke detector on one of the inputs of an input comparator circuit which provides static input protection and a high input impedance by employing thick oxide layer over the gates of the comparator transistors. The CMOS chip also directly supplies operating current for a mechanical or piezoelectric horn. Further features include a clocked low voltage alarm; a buffer stage to permit the interconnection of a number of different detector circuits in common to a single input/output lead; and a visual LED indicator to indicate that the circuit is operating and to provide a visual indication any time the alarm condition for the circuit has been actuated.

Abstract: A detection circuit particularly adapted as a smoke detector employes a minimum number of components by a CMOS integrated circuit which receives directly the output of a smoke detector on one of the inputs of an input comparator circuit which provides static input protection and a high input impedence by employing thick oxide layer over the gates of the comparator transistors. The CMOS chip also directly supplies operating current for a mechanical or piezoelectric horn. Further features include a clocked low voltage alarm; a buffer stage to permit the interconnection of a number of different detector circuits in common to a single input/output lead; and a visual LED indicator to indicate that the circuit is operating and to provide a visual indication any time the alarm condition for the circuit has been actuated.

Abstract: A detection circuit particularly adapted as a smoke detector employs a minimum number of components by a CMOS integrated circuit which receives directly the output of a smoke detector on one of the inputs of an input comparator circuit which provides static input protection and a high input impedance by employing thick oxide layer over the gates of the comparator transistors. The CMOS chip also directly supplies operating current for a mechanical or piezoelectric horn. Further features include a clocked low voltage alarm; a buffer stage to permit the interconnection of a number of different detector circuits in common to a single input/output lead; and a visual LED indicator to indicate that the circuit is operating and to provide a visual indication any time the alarm condition for the circuit has been actuated.