Patents by Inventor Robert L. Franch

Robert L. Franch has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20090295449
    Abstract: A circuit and method for measuring duty cycle uncertainty in an on-chip global clock. A global clock is provided to a delay line at a local clock buffer. Delay line taps (inverter outputs) are inputs to a register that is clocked by the local clock buffer. The register captures clock edges, which are filtered to identify a single location for each edge. Imbalance in space between the edges indicated imbalance in duty cycle. Up/down signals are generated from any imbalance and passed to a phase locked loop to adjust the balance.
    Type: Application
    Filed: August 12, 2009
    Publication date: December 3, 2009
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Robert C. Dixon, Robert L. Franch, Phillip J. Restle
  • Publication number: 20080309364
    Abstract: A method and circuit for measuring internal pulses includes an enable circuit configured to receive a control signal from an on-chip built-in tester to enable measurement of internal circuits. A delay chain is configured to receive a pulse signal from an on-chip circuit component. Sampling latches each include a data input coupled between adjacent delay elements of the delay chain and synchronized with the clock signal such that a transition in the pulse signal is indicated by comparing adjacent digital values in an output sequence.
    Type: Application
    Filed: June 12, 2007
    Publication date: December 18, 2008
    Inventors: Rajiv V. Joshi, Robert L. Franch, Robert Maurice Houle, Kevin A. Batson
  • Patent number: 7459940
    Abstract: A Local Clock Buffer (LCB), an IC chip including registers, some of which may include master/slave latches, locally clocked by the LCB, e.g., providing a launch clock and a capture clock each with an identified critical edge. The LCB includes asymmetrically inductively peaked series connected logic gates (e.g., inverters and/or NAND gates), each with an inductor between gate devices and supply (Vdd) or ground. The series connected gates alternate between having the inductor located between gate devices and the supply and located between gate devices and ground, providing asymmetric inductive peaking to maintain the sharpness of the critical edges. Optionally, corresponding logic gates in multiple LCBs may share the same inductor. Asymmetric inductive peaking allows reducing LCB power without degrading performance.
    Type: Grant
    Filed: April 2, 2007
    Date of Patent: December 2, 2008
    Assignee: International Business Machines Corporation
    Inventor: Robert L. Franch
  • Publication number: 20080290893
    Abstract: A Local Clock Buffer (LCB), an IC chip including registers, some of which may include master/slave latches, locally clocked by the LCB, e.g., providing a launch clock and a capture clock each with an identified critical edge. The LCB includes asymmetrically inductively peaked series connected logic gates (e.g., inverters and/or NAND gates), each with an inductor between gate devices and supply (Vdd) or ground. The series connected gates alternate between having the inductor located between gate devices and the supply and located between gate devices and ground, providing asymmetric inductive peaking to maintain the sharpness of the critical edges. Optionally, corresponding logic gates in multiple LCBs may share the same inductor. Asymmetric inductive peaking allows reducing LCB power without degrading performance.
    Type: Application
    Filed: August 4, 2008
    Publication date: November 27, 2008
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Robert L. Franch
  • Publication number: 20080291970
    Abstract: A device temperature measurement circuit, an integrated circuit (IC) including a device temperature measurement circuit, a method of characterizing device temperature and a method of monitoring temperature. The circuit includes a constant current source and a clamping device. The clamping device selectively shunts current from the constant current source or allows the current to flow through a PN junction, which may be the body to source/drain junction of a field effect transistor (FET). Voltage measurements are taken directly from the PN junction. Junction temperature is determined from measured junction voltage.
    Type: Application
    Filed: July 22, 2008
    Publication date: November 27, 2008
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPERATION
    Inventors: Robert L. Franch, Keith A. Jenkins
  • Patent number: 7452128
    Abstract: A device temperature measurement circuit, an integrated circuit (IC) including a device temperature measurement circuit, a method of characterizing device temperature and a method of monitoring temperature. The circuit includes a constant current source and a clamping device. The clamping device selectively shunts current from the constant current source or allows the current to flow through a PN junction, which may be the body to source/drain junction of a field effect transistor (FET). Voltage measurements are taken directly from the PN junction. Junction temperature is determined from measured junction voltage.
    Type: Grant
    Filed: May 11, 2007
    Date of Patent: November 18, 2008
    Assignee: International Business Machines Corporation
    Inventors: Robert L. Franch, Keith A. Jenkins
  • Publication number: 20080238484
    Abstract: A Local Clock Buffer (LCB), an IC chip including registers, some of which may include master/slave latches, locally clocked by the LCB, e.g., providing a launch clock and a capture clock each with an identified critical edge. The LCB includes asymmetrically inductively peaked series connected logic gates (e.g., inverters and/or NAND gates), each with an inductor between gate devices and supply (Vdd) or ground. The series connected gates alternate between having the inductor located between gate devices and the supply and located between gate devices and ground, providing asymmetric inductive peaking to maintain the sharpness of the critical edges. Optionally, corresponding logic gates in multiple LCBs may share the same inductor. Asymmetric inductive peaking allows reducing LCB power without degrading performance.
    Type: Application
    Filed: April 2, 2007
    Publication date: October 2, 2008
    Inventor: Robert L. Franch
  • Publication number: 20080198700
    Abstract: A circuit for measuring timing uncertainty in a clocked digital path and in particular, the number of logic stages completed in any clock cycle. A local clock buffer receives a global clock and provides a complementary pair of local clocks. A first local (launch) clock is an input to a delay line, e.g., 3 clock cycles worth of series connected inverters. Delay line taps (inverter outputs) are inputs to a register that is clocked by the complementary clock pair to capture progression of the launch clock through the delay line and identify any variation (e.g., from jitter, VDD noise) in that progression. Global clock skew and across chip gate length variation can be measured by cross coupling launch clocks from a pair of such clock buffers and selectively passing the local and remote launch clocks to the respective delay lines.
    Type: Application
    Filed: March 10, 2008
    Publication date: August 21, 2008
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Robert L. Franch, William V. Huott, Norman K. James, Phillip J. Restle, Timothy M. Skergan
  • Publication number: 20080198699
    Abstract: A circuit for measuring timing uncertainty in a clocked digital path and in particular, the number of logic stages completed in any clock cycle. A local clock buffer receives a global clock and provides a complementary pair of local clocks. A first local (launch) clock is an input to a delay line, e.g., 3 clock cycles worth of series connected inverters. Delay line taps (inverter outputs) are inputs to a register that is clocked by the complementary clock pair to capture progression of the launch clock through the delay line and identify any variation (e.g., from jitter, VDD noise) in that progression. Global clock skew and across chip gate length variation can be measured by cross coupling launch clocks from a pair of such clock buffers and selectively passing the local and remote launch clocks to the respective delay lines.
    Type: Application
    Filed: March 10, 2008
    Publication date: August 21, 2008
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Robert L. Franch, William V. Huott, Norman K. James, Phillip J. Restle, Timothy M. Skergan
  • Publication number: 20080186035
    Abstract: A device temperature measurement circuit, an integrated circuit (IC) including a device temperature measurement circuit, a method of characterizing device temperature and a method of monitoring temperature. The circuit includes a constant current source and a clamping device. The clamping device selectively shunts current from the constant current source or allows the current to flow through a PN junction, which may be the body to source/drain junction of a field effect transistor (FET). Voltage measurements are taken directly from the PN junction. Junction temperature is determined from measured junction voltage.
    Type: Application
    Filed: April 3, 2008
    Publication date: August 7, 2008
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPERATION
    Inventors: Robert L. Franch, Keith A. Jenkins
  • Publication number: 20080187024
    Abstract: A device temperature measurement circuit, an integrated circuit (IC) including a device temperature measurement circuit, a method of characterizing device temperature and a method of monitoring temperature. The circuit includes a constant current source and a clamping device. The clamping device selectively shunts current from the constant current source or allows the current to flow through a PN junction, which may be the body to source/drain junction of a field effect transistor (FET). Voltage measurements are taken directly from the PN junction. Junction temperature is determined from measured junction voltage.
    Type: Application
    Filed: April 3, 2008
    Publication date: August 7, 2008
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPERATION
    Inventors: Robert L. Franch, Keith A. Jenkins
  • Patent number: 7400555
    Abstract: A circuit for measuring timing uncertainty in a clocked digital path and in particular, the number of logic stages completed in any clock cycle. A local clock buffer receives a global clock and provides a complementary pair of local clocks. A first local (launch) clock is an input to a delay line, e.g., 3 clock cycles worth of series connected inverters. Delay line taps (inverter outputs) are inputs to a register that is clocked by the complementary clock pair to capture progression of the launch clock through the delay line and identify any variation (e.g., from jitter, VDD noise) in that progression. Global clock skew and across chip gate length variation can be measured by cross coupling launch clocks from a pair of such clock buffers and selectively passing the local and remote launch clocks to the respective delay lines.
    Type: Grant
    Filed: November 13, 2003
    Date of Patent: July 15, 2008
    Assignee: International Business Machines Corporation
    Inventors: Robert L. Franch, William V. Huott, Norman K. James, Phillip J. Restle, Timothy M. Skergan
  • Patent number: 7255476
    Abstract: A device temperature measurement circuit, an integrated circuit (IC) including a device temperature measurement circuit, a method of characterizing device temperature and a method of monitoring temperature. The circuit includes a constant current source and a clamping device. The clamping device selectively shunts current from the constant current source or allows the current to flow through a PN junction, which may be the body to source/drain junction of a field effect transistor (FET). Voltage measurements are taken directly from the PN junction. Junction temperature is determined from measured junction voltage.
    Type: Grant
    Filed: April 14, 2004
    Date of Patent: August 14, 2007
    Assignee: International Business Machines Corporation
    Inventors: Robert L. Franch, Keith A. Jenkins
  • Patent number: 5212616
    Abstract: An improved latch-up protection circuit is disclosed which prevents damage to a CMOS integrated circuit chip due to transient surges or internal-circuitry initiated latch-ups and which clears any latch-up condition or SCR mode. In each embodiment, the latch-up protection circuit is integrated with an on-chip voltage regulation circuit which provides on-chip power to the internal chip circuitry. A first approach to implementing the latch-up protection circuit is to detect an average current through the power transistor of the voltage regulation circuit over a few microseconds. Should the average current exceed a preset value, then the power transistor is turned off and the power (V.sub.DDI) supplied to the internal chip circuitry is reduced to zero, thereby removing the latch-up condition. In a second approach, the on-chip voltage (V.sub.DDI) supplied to internal chip circuitry is compared with a reference voltage signal representative of the occurrence of a latch-up condition, i.e.
    Type: Grant
    Filed: October 23, 1991
    Date of Patent: May 18, 1993
    Assignee: International Business Machines Corporation
    Inventors: Sang H. Dhong, Robert L. Franch
  • Patent number: 5157634
    Abstract: A DRAM is described including a plurality of operable storage cells, each cell including a capacitance for storing a charge indicative of data. The charge tends to dissipate below an acceptable level after a predetermined time interval T1 for a majority of the operable cells and for a minority of the operable cells, it dissipates below the acceptable level after a shorter time interval T2. The time between DRAM refresh cycles is adjusted so as to be greater than time interval T2. The DRAM comprises: a plurality of redundant storage cells; a decoder for receiving the address of an operable memory cell and providing a first output if the address indicates one of the operable cells of the minority of cells and a second output if the address indicates one of the operable cells of the majority. A switching circuit is responsive to the first output to enable access of a redundant stoarge cell and to prevent access of the minority storage cell.
    Type: Grant
    Filed: October 23, 1990
    Date of Patent: October 20, 1992
    Assignee: International Business Machines Corporation
    Inventors: Sang H. Dhong, Robert L. Franch, Wei Hwang