Abstract: A system and method for calibration of a test socket using a composite waveform. A group of input signal pins of test system are coupled together. A pin belonging to the group is selected as a pin under calibration. A first calibration edge is applied to the pin under calibration. After a delay, a group of complementary edges is applied to the remaining pins of the group. As a result of the coupling of the pins, a response comprising a reflected edge and a transmitted combined edge are produced, which overlap to form a composite waveform. A comparator is used to detect an observable feature in the composite waveform to obtain timing information with respect to the pin under calibration and the remaining pins of the group. Each pin may be analyzed in turn, and the group of pins calibrated using the acquired information.

Abstract: A system and method for calibration of a test socket using a composite waveform. A group of input signal pins of test system are coupled together. A pin belonging to the group is selected as a pin under calibration. A first calibration edge is applied to the pin under calibration. After a delay, a group of complementary edges is applied to the remaining pins of the group. As a result of the coupling of the pins, a response comprising a reflected edge and a transmitted combined edge are produced, which overlap to form a composite waveform. A comparator is used to detect an observable feature in the composite waveform to obtain timing information with respect to the pin under calibration and the remaining pins of the group. Each pin may be analyzed in turn, and the group of pins calibrated using the acquired information.

Abstract: A test system memory architecture for passing parameters and testing dynamic components includes a main memory 15, a mask memory 20, and a definition memory 25, operating under control of a main sequence control memory 18. A corresponding subroutine memory 38, subroutine mask memory 22, and subroutine definition memory 27 operate under control of a subroutine sequence control memory 33. Multiplexing apparatus is used to selectively connect any of these memories to the formatter circuit 10. In addition, the architecture includes a parameter enabling memory 30 which is coupled to the subroutine SCM 33 and a switching means for controlling which of the subroutine memory 38 or main memory 15 is coupled to the formatter circuit 10.

Abstract: In an automatic test system, a dynamically controllable addressing circuit coupled to an address bus and a data bus includes a first register 10 for storing a fixed address, a programmable address register 12 connected to store address information from the data bus when the fixed address in the first register corresponds to address information on the address bus, and a programmable data register 18 connected to store data from the data bus when the address information in the programmable address register 12 corresponds to the address information on the address bus. In the preferred embodiment the address bus and the first register are connected through an exclusive or gate 14 to control the operation of the programmable address register 12. A second exclusive or gate 16 is connected between the address bus and the programmable address register 12 to control the operation of the programmable data register 18.