Abstract: In an implementation of latent error detection, memory regions that each correspond to a different processor element of a redundant processor system are scanned for latent processing errors maintained as erroneous data. The data maintained in the memory regions is compared to detect a latent processing error in a first memory region. The latent processing error is resolved by copying data from a second memory region into the first memory region where the data maintained in the second memory region is determined to be identical to data maintained in at least a third memory region.

Abstract: A computer system includes a primary processor and a secondary processor running in lockstep. The lockstep may or may not be synchronous. Errors occurring in the primary processor or the secondary processor are reported to an error-handling module. If the error is a recoverable error, the state of one of the processors is saved and the processors are restarted using the saved state. In addition to the reporting of errors from the processors, cross checking of the operation of the processors is performed to detect a divergence in the operation of the processors. If the divergence is reported to be due to a recoverable error, the state of the one of the processors is saved and the processors are restarted using the saved state. Procedures are also disclosed to ensure that data corruption does not propagate onto an associated network, and to ensure that the system is not lost as a network resource during processor restart.

Abstract: An apparatus and protocol to determine the group of processors that will survive communications faults and/or timed-event failures in a distributed multiprocessor or clustered system. The processors are coupled to one another by an inter-processor communication network that is used, inter alia, by each processor to send path probe messages to each of the other processor units on all available network paths. A processor is suspected of being communicatively isolated, or having ceased operations, when one or more of the other processors detects the absence of an acknowledgment response from the processor. When this happens, all of the processors are subjected to a series of stages in which they repeatedly broadcast their status and connectivity to each other.

Abstract: A redundant system includes a primary process and a backup process. The system is configured to conduct online software replacement by sending an instruction to the backup process to terminate, and then starting a replacement backup process using an updated code version. Tokenized checkpoints are provided to the replacement backup process from the primary process, the tokenized checkpoints including a basic data structure and a token data structure. The token data structure includes one or more tokens that may be considered or may be ignored by the replacement backup process. After the state of the replacement backup process has been established, the replacement backup process is designated to be the new primary process. At that time, a new backup process is started using the updated code.

Abstract: A computer system includes a primary processor and a secondary processor running in lockstep. The lockstep may or may not be synchronous. Errors occurring in the primary processor or the secondary processor are reported to an error-handling module. If the error is a recoverable error, the state of one of the processors is saved and the processors are restarted using the saved state. In addition to the reporting of errors from the processors, cross checking of the operation of the processors is performed to detect a divergence in the operation of the processors. If the divergence is reported to be due to a recoverable error, the state of the one of the processors is saved and the processors are restarted using the saved state. Procedures are also disclosed to ensure that data corruption does not propagate onto an associated network, and to ensure that the system is not lost as a network resource during processor restart.

Abstract: A logical processor is formed from a pair of processor units operating in close synchrony to perform self-check operations. Outputs of one of the processor units are compared to that of the other processor unit. When one of the processor units experiences an error, creating a divergence, that error and/or divergence will be made known to the Master processor which will then determine if recovery from the error can be made and, if so, save its processing state to memory, cause a reset of both processor units to an initial state to begin executing reinitialization code using the prior saved state for both processor units.

Abstract: A scalable clustered system includes a global fabric, and two or more cluster nodes interconnected via the global fabric. Each cluster node includes a node naming agent (NNA), a local fabric and one or more end nodes interconnected via the local fabric. The NNA is configured as a fully symmetrical translation device interposed between the local fabric and the global fabric. The NNA provides support for scaled clustering by transforming a local/global cluster address into a corresponding global/local cluster address for each packet in an outbound/inbound path. As embodied and broadly described herein, the invention relates also to a method including steps for scaling the clustered system. Additionally, the invention relates to a computer readable medium in a scalable clustered system that embodies computer program code configured to cause that system to perform steps for configuring and scaling that system.

Abstract: A system and method for controlling network traffic flow in a multi-processor network is disclosed. The method employs a two-part algorithm to determine when it is appropriate for a client node to transmit data over a network to one or more server nodes. The first part of the algorithm calls for the client node to transmit data over the network after receiving an acknowledgement from one or more of the server nodes to which data transfer is outstanding. The second part of the algorithm provides for the client node transmitting data over the network after a predetermined time interval has elapsed since a data transmission. The time interval is based, in part, on the length of outstanding data packets and a statistical analysis of the number of nodes transmitting or receiving data packets. The transmission of data over the network is accomplished by a hybrid scheme, comprising a combination of PUSH and PULL transmission protocols.

Abstract: An apparatus and method for tolerating failure of the AC power source in a power supply switchable between the AC power source and a battery, in a processor system having a set of one or more components subject to being powered down. When the failure of the AC power source is recognized, the power supply is switched from the AC power source to the battery. For a first period of time, the battery powers the processor system with all components powered on. The battery then powers the processor system with the specific set of components powered off for a second period of time. In one embodiment, a determination is made that the battery can power the processor system with the set of components powered down for a predetermined period of time. A determination of the first period of time is then made as the capacity of the battery exceeding the predetermined period of time, if the excess capacity is used to power the processor system with the set of components powered on.

Abstract: A system for issuing a family of instructions during a single clock includes a decoder for decoding the family of instructions and logic, responsive to the decode result, for determining whether resource conflicts would occur if the family were issued during one clock. If no resource conflicts occur, an execution unit executes the family regardless of whether dependencies among the instructions in the family exist.

Abstract: A split brain avoidance protocol to determine the group of processors that will survive a complete partitioning (disconnection) in the inter-processor communications paths connecting processors in a multi-processor system. Processors embodying the invention detect that the set of processors with which they can communicate has changed. They then choose either to halt or to continue operations, guided by the goal of minimizing the possibility that multiple disconnected groups of processors continue to operate as independent systems, each group having determined (incorrectly) that the processors of the other groups have failed.

Abstract: Multiple processors are connected to form a multiprocessor system having interprocessor communicating capability. In the face of a power-fail signal, indicating that possible power loss is imminent, a processor will proceed through a shut-down procedure to save the present operating state so that when power is re-applied the processor can continue from the operating state it left when power was lost. The shut-down procedure concludes with the processor broadcasting messages to all other processors that it is undergoing a power-fail shut-down which is noted by the other processors to later cause them to enter a cautious mode of operation so as to not exclude the processor in any system configuration involving agreement of all processors by reason of the processor's loss of power.

Abstract: An apparatus and protocol to determine the group of processors that will survive communications faults and/or timed-event failures in a multiprocessor system. The processors each have a respective memory, and the processors are coupled by means of an inter-processor communication network. The processors detect that the set of processors with which they can communicate has changed. They can choose to either halt or continue operations based on minimizing the likelihood that disconnected groups of processors will continue to operate as independent systems. The processors construct a connectivity matrix on the initiation of a regroup operation. The connectivity information is used to ensure that all the processors in the final group that survives can communicate with all other processors in the group. One or more processors may halt to achieve this characteristic.

Abstract: A computing system develops time/date values by using a free-running counter to measure and accumulate increments of time. The increments of time are converted from the resolution of the free-running counter to that used for the time and date values by dividing by a conversion variable and then used to update the time/date value. The accuracy of the time/date value is monitored by periodically comparing the rate of the free-running counter to the rate of a more accurate, external clock. The ratio of these two rates is used to adjust the conversion variable. The conversion variable reflects any differences between (1) the rate of change of the increments of time used for developing the time/data value and (2) the external clock. Its use here, therefore, will operate to either slow down or speed up the rate of change of the time/date value so that it more closely tracks the external clock.

Abstract: Multiple processors are connected to form a multiprocessor system having inter-processor communicating capability. Each processor maintains a configuration option register indicating the resources necessary to operate the multiprocessor system. In the event of a power-fail signal, indicating that possible power loss is imminent, a processor will proceed through a shut-down procedure to save the present operating state so that when power is re-applied the processor can continue from the operating state it left when power was lost. Those processors not receiving a power-fail signal will attempt to reconfigure the multiprocessor system, waiting a reasonable amount of time for the processor receiving the power-fail signal to continue operations. If the processor has not recovered from the power-fail signal after a reasonable amount of time, the other processors check the configuration option register to determine whether that processor is necessary for operation of the multiprocessor system.

Abstract: A system providing a multiple number of virtual channels in a computer system having a smaller number of physical channels. Multiple queues are provided that are mapped to channels. The mapping of the queues to the channels changes depending on the message traffic and priority of the queues. Queues of lower priority are preempted if a higher priority queue needs a channel.

Abstract: A mechanism for handling exceptions in a processor system that issues a family of more than one instruction during a single clock that utilizes the exception handling procedures developed for single instructions. The mechanism detects an exception associated with one of the instructions in the family, inhibits the data writes for the instructions in the family, flushes the pipeline, and reissues the instruction singly. The exception handling procedure for the single instruction may then be utilized.

Abstract: A branch recovery mechanism completes the processing of a concurrently issued family of instructions depending on the location of the branch instruction in the family and on whether the branch was correctly predicted. If the branch was not correctly predicted, the writes and stores of instructions in the family the precede the branch instruction are completed and those instructions are retired. However, the writes and stores of the instructions in the family following the branch instruction are inhibited.

Abstract: In a data processing system, a multiplication operation is immediately followed by a redundant multiplication operation, using the same, albeit altered, operands, to check the initial result. The initial result is immediately available for use, but the check is not performed until some time later. The original operands are altered for the redundant multiplication operation by shifting one operand 1 bit, and swapping them before multiplication.