Patents by Inventor Robert L. Jarecki, Jr.

Robert L. Jarecki, Jr. has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10025123
    Abstract: The various technologies presented herein relate to various hybrid phononic-photonic waveguide structures that can exhibit nonlinear behavior associated with traveling-wave forward stimulated Brillouin scattering (forward-SBS). The various structures can simultaneously guide photons and phonons in a suspended membrane. By utilizing a suspended membrane, a substrate pathway can be eliminated for loss of phonons that suppresses SBS in conventional silicon-on-insulator (SOI) waveguides. Consequently, forward-SBS nonlinear susceptibilities are achievable at about 3000 times greater than achievable with a conventional waveguide system. Owing to the strong phonon-photon coupling achievable with the various embodiments, potential application for the various embodiments presented herein cover a range of radiofrequency (RF) and photonic signal processing applications. Further, the various embodiments presented herein are applicable to applications operating over a wide bandwidth, e.g. 100 MHz to 50 GHz or more.
    Type: Grant
    Filed: December 15, 2015
    Date of Patent: July 17, 2018
    Assignees: National Technology & Engineering Solutions of Sandia, LLC
    Inventors: Peter Thomas Rakich, Heedeuk Shin, Ryan Camacho, Jonathan Albert Cox, Robert L. Jarecki, Jr., Wenjun Qiu, Zheng Wang
  • Patent number: 9696492
    Abstract: A radio-frequency photonic devices employs photon-phonon coupling for information transfer. The device includes a membrane in which a two-dimensionally periodic phononic crystal (PnC) structure is patterned. The device also includes at least a first optical waveguide embedded in the membrane. At least a first line-defect region interrupts the PnC structure. The first optical waveguide is embedded within the line-defect region.
    Type: Grant
    Filed: March 3, 2016
    Date of Patent: July 4, 2017
    Assignee: National Technology & Engineering Solutions of Sandia, LLC
    Inventors: Jonathan Albert Cox, Robert L. Jarecki, Jr., Peter Thomas Rakich, Zheng Wang, Heedeuk Shin, Aleem Siddiqui, Andrew Lea Starbuck
  • Patent number: 9659797
    Abstract: Wafer scale oblique angle etching of a semiconductor substrate is performed in a conventional plasma etch chamber by using a fixture that supports a multiple number of separate Faraday cages. Each cage is formed to include an angled grid surface and is positioned such that it will be positioned over a separate one of the die locations on the wafer surface when the fixture is placed over the wafer. The presence of the Faraday cages influences the local electric field surrounding each wafer die, re-shaping the local field to be disposed in alignment with the angled grid surface. The re-shaped plasma causes the reactive ions to follow a linear trajectory through the plasma sheath and angled grid surface, ultimately impinging the wafer surface at an angle. The selected geometry of the Faraday cage angled grid surface thus determines the angle at with the reactive ions will impinge the wafer.
    Type: Grant
    Filed: September 17, 2014
    Date of Patent: May 23, 2017
    Assignee: Sandia Corporation
    Inventors: David Bruce Burckel, Robert L. Jarecki, Jr., Patrick Sean Finnegan
  • Patent number: 9632261
    Abstract: An optoelectronic device package and a method for its fabrication are provided. The device package includes a lid die and an active die that is sealed or sealable to the lid die and in which one or more optical waveguides are integrally defined. The active die includes one or more active device regions, i.e. integral optoelectronic devices or etched cavities for placement of discrete optoelectronic devices. Optical waveguides terminate at active device regions so that they can be coupled to them. Slots are defined in peripheral parts of the active dies. At least some of the slots are aligned with the ends of integral optical waveguides so that optical fibers or optoelectronic devices inserted in the slots can optically couple to the waveguides.
    Type: Grant
    Filed: August 5, 2015
    Date of Patent: April 25, 2017
    Assignee: Sandia Corporation
    Inventors: William A. Zortman, Michael David Henry, Robert L. Jarecki, Jr.
  • Patent number: 9268092
    Abstract: The various technologies presented herein relate to various hybrid phononic-photonic waveguide structures that can exhibit nonlinear behavior associated with traveling-wave forward stimulated Brillouin scattering (forward-SBS). The various structures can simultaneously guide photons and phonons in a suspended membrane. By utilizing a suspended membrane, a substrate pathway can be eliminated for loss of phonons that suppresses SBS in conventional silicon-on-insulator (SOI) waveguides. Consequently, forward-SBS nonlinear susceptibilities are achievable at about 3000 times greater than achievable with a conventional waveguide system. Owing to the strong phonon-photon coupling achievable with the various embodiments, potential application for the various embodiments presented herein cover a range of radiofrequency (RF) and photonic signal processing applications. Further, the various embodiments presented herein are applicable to applications operating over a wide bandwidth, e.g. 100 MHz to 50 GHz or more.
    Type: Grant
    Filed: October 16, 2013
    Date of Patent: February 23, 2016
    Assignee: Sandia Corporation
    Inventors: Robert L. Jarecki, Jr., Peter Thomas Rakich, Ryan Camacho, Heedeuk Shin, Jonathan Albert Cox, Wenjun Qiu, Zheng Wang
  • Patent number: 9190392
    Abstract: A 3D stacked sASIC is provided that includes a plurality of 2D reconfigurable structured structured ASIC (sASIC) levels interconnected through hard-wired arrays of 3D vias. The 2D sASIC levels may contain logic, memory, analog functions, and device input/output pad circuitry. During fabrication, these 2D sASIC levels are stacked on top of each other and fused together with 3D metal vias. Such 3D vias may be fabricated as through-silicon vias (TSVs). They may connect to the back-side of the 2D sASIC level, or they may be connected to top metal pads on the front-side of the 2D sASIC level.
    Type: Grant
    Filed: May 20, 2014
    Date of Patent: November 17, 2015
    Assignee: Sandia Corporation
    Inventors: Subhash L. Shinde, John Teifel, Richard S. Flores, Robert L. Jarecki, Jr., Todd Bauer
  • Patent number: 6210594
    Abstract: A near substrate reactant homogenization apparatus reduces the excess reactive species in a region at or near the edge of a substrate surface to provide a uniform reactant concentration over the substrate, thereby improving etch rate uniformity over the substrate. The near substrate reactant homogenization apparatus has a substantially planar surface that is parallel to said substrate surface and that extends beyond the substrate edge, at or below the substrate surface. In a first preferred embodiment of the invention, the temperature of the gas absorber area is changed to promote recombination or condensation of excess reactive species at the substrate edge, where the excess species are removed. In another, equally preferred embodiment of the invention, the gas absorber area is formed of a porous material having a large surface area. Excess reactive species enter the porous structure and are subsequently recombined.
    Type: Grant
    Filed: February 26, 1998
    Date of Patent: April 3, 2001
    Assignee: Applied Materials, Inc.
    Inventors: Zabra H. Amini, Robert B. Campbell, Robert L. Jarecki, Jr., Gary D. Tipton
  • Patent number: 5938943
    Abstract: A near substrate reactant homogenization apparatus reduces the excess reactive species in a region at or near the edge of a substrate surface to provide a uniform reactant concentration over the substrate, thereby improving etch rate uniformity over the substrate. The near substrate reactant homogenization apparatus has a substantially planar surface that is parallel to said substrate surface and that extends beyond the substrate edge, at or below the substrate surface. In a first preferred embodiment of the invention, the temperature of the gas absorber area is changed to promote recombination or condensation of excess reactive species at the substrate edge, where the excess species are removed. In another, equally preferred embodiment of the invention, the gas absorber area is formed of a porous material having a large surface area. Excess reactive species enter the porous structure and are subsequently recombined.
    Type: Grant
    Filed: July 28, 1995
    Date of Patent: August 17, 1999
    Assignee: Applied Materials, Inc.
    Inventors: Zahra H. Amini, Robert B. Campbell, Robert L. Jarecki, Jr., Gary D. Tipton