Patents by Inventor Robert L. KRAUSE

Robert L. KRAUSE has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • ACUTE HEALTH EVENT MONITORING AND ALERTING
    Publication number: 20240123238
    Abstract: A system comprising processing circuitry configured to receive a wirelessly-transmitted message from a medical device, the message indicating that the medical device detected an acute health event of the patient. In response to the message, the processing circuitry is configured to determine a location of the patient, determine an alert area based on the location of the patient, and control transmission of an alert of the acute heath event of the patient to any one or more computing devices of one or more potential responders within the alert area.
    Type: Application
    Filed: February 16, 2022
    Publication date: April 18, 2024
    Inventors: Robert W. Stadler, Becky L. Dolan, Yong K. Cho, Paul G. Krause, Shantanu Sarkar, Robert C. Kowal
  • Isolation between semiconductor components
    Patent number: 10446498
    Abstract: In some general aspects, an apparatus may include a first semiconductor die, a second semiconductor die, and a capacitive isolation circuit being coupled to the first semiconductor die and the second semiconductor die. The capacitive isolation circuit may be disposed outside of the first semiconductor die and the second semiconductor die. The first semiconductor die, the second semiconductor die, and the capacitive circuit may be included in a molding of a semiconductor package.
    Type: Grant
    Filed: August 14, 2017
    Date of Patent: October 15, 2019
    Assignee: Fairchild Semiconductor Corporation
    Inventors: John Constantino, Timwah Luk, Ahmad Ashrafzadeh, Robert L. Krause, Etan Shacham, Maria Clemens Ypil Quinones, Janusz Bryzek, Chung-Lin Wu
  • ISOLATION BETWEEN SEMICONDUCTOR COMPONENTS
    Publication number: 20170373008
    Abstract: In some general aspects, an apparatus may include a first semiconductor die, a second semiconductor die, and a capacitive isolation circuit being coupled to the first semiconductor die and the second semiconductor die. The capacitive isolation circuit may be disposed outside of the first semiconductor die and the second semiconductor die. The first semiconductor die, the second semiconductor die, and the capacitive circuit may be included in a molding of a semiconductor package.
    Type: Application
    Filed: August 14, 2017
    Publication date: December 28, 2017
    Applicant: FAIRCHILD SEMICONDUCTOR CORPORATION
    Inventors: John CONSTANTINO, Timwah LUK, Ahmad ASHRAFZADEH, Robert L. KRAUSE, Etan SHACHAM, Maria Clemens Ypil QUINONES, Janusz BRYZEK, Chung-Lin WU
  • Isolation between semiconductor components
    Patent number: 9735112
    Abstract: In some general aspects, an apparatus may include a first semiconductor die, a second semiconductor die, and a capacitive isolation circuit being coupled to the first semiconductor die and the second semiconductor die. The capacitive isolation circuit may be disposed outside of the first semiconductor die and the second semiconductor die. The first semiconductor die, the second semiconductor die, and the capacitive circuit may be included in a molding of a semiconductor package.
    Type: Grant
    Filed: January 9, 2015
    Date of Patent: August 15, 2017
    Assignee: Fairchild Semiconductor Corporation
    Inventors: John Constantino, Timwah Luk, Ahmad Ashrafzadeh, Robert L. Krause, Etan Shacham, Maria Clemens Ypil Quinones, Janusz Bryzek, Chung-Lin Wu
  • ISOLATION BETWEEN SEMICONDUCTOR COMPONENTS
    Publication number: 20150200162
    Abstract: In some general aspects, an apparatus may include a first semiconductor die, a second semiconductor die, and a capacitive isolation circuit being coupled to the first semiconductor die and the second semiconductor die. The capacitive isolation circuit may be disposed outside of the first semiconductor die and the second semiconductor die. The first semiconductor die, the second semiconductor die, and the capacitive circuit may be included in a molding of a semiconductor package.
    Type: Application
    Filed: January 9, 2015
    Publication date: July 16, 2015
    Inventors: John CONSTANTINO, Timwah LUK, Ahmad ASHRAFZADEH, Robert L. KRAUSE, Etan SHACHAM, Maria Clemens Ypil QUINONES, Janusz BRYZEK, Chung-Lin WU