Patents by Inventor Robert L. Payne

Robert L. Payne has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11946023
    Abstract: An enzymatically produced ?-glucan oligomer/polymer compositions is provided. The enzymatically produced ?-glucan oligomer/polymers can be derivatized into ?-glucan ether compounds. The ?-glucan oligomers/polymers and the corresponding ?-glucan ethers are cellulose and/or protease resistant, making them suitable for use in fabric care and laundry care applications. Methods for the production and use of the present compositions are also provided.
    Type: Grant
    Filed: January 28, 2022
    Date of Patent: April 2, 2024
    Assignee: Nutrition & Biosciences USA 4, Inc.
    Inventors: Robert DiCosimo, Qiong Cheng, Rakesh Nambiar, Jayme L. Paullin, Mark S. Payne, Jahnavi Chandra Prasad, Zheng You
  • Patent number: 8517077
    Abstract: The invention generally relates to an automatic taper for drywall. More specifically, the invention relates to a manner for accessing the interior of the business end of the automatic taper for drywall. The taper may have an easily removable cover plate which may allow a user to obtain easy access to the interior of the nozzle of the taper. A user may gain access to the interior of the nozzle by flipping a rotating securing bar upward and then removing the removable cover plate.
    Type: Grant
    Filed: May 26, 2011
    Date of Patent: August 27, 2013
    Assignee: Drywall Master Tools, Inc.
    Inventor: Robert L. Payne
  • Patent number: 8381789
    Abstract: An automatic drywall taper is provided. The automatic drywall taper has a securing device for securing drywall tape to the body of the taper during use. The securing device has an elongated bar which runs substantially parallel to the body of the taper. The elongated bar is spring activated to lock a hub on a bar which is attached substantially perpendicular to the body of the taper. The hub rotates thereby allowing the tape to dispense and be used on drywall. The hub has a braking mechanism which allows for the controlled release of the tape.
    Type: Grant
    Filed: February 11, 2011
    Date of Patent: February 26, 2013
    Assignee: Drywall Master Tools, Inc.
    Inventor: Robert L. Payne
  • Publication number: 20110290422
    Abstract: The invention generally relates to an automatic taper for drywall. More specifically, the invention relates to a manner for accessing the interior of the business end of the automatic taper for drywall. The taper may have an easily removable cover plate which may allow a user to obtain easy access to the interior of the nozzle of the taper. A user may gain access to the interior of the nozzle by flipping a rotating securing bar upward and then removing the removable cover plate.
    Type: Application
    Filed: May 26, 2011
    Publication date: December 1, 2011
    Inventor: Robert L. Payne
  • Publication number: 20110198039
    Abstract: An automatic drywall taper is provided. The automatic drywall taper has a securing device for securing drywall tape to the body of the taper during use. The securing device has an elongated bar which runs substantially parallel to the body of the taper. The elongated bar is spring activated to lock a hub on a bar which is attached substantially perpendicular to the body of the taper. The hub rotates thereby allowing the tape to dispense and be used on drywall. The hub has a braking mechanism which allows for the controlled release of the tape.
    Type: Application
    Filed: February 11, 2011
    Publication date: August 18, 2011
    Inventor: Robert L. Payne
  • Publication number: 20100174521
    Abstract: Various aspects of the present invention are directed to design modeling and/or processing of streaming data. According to an example embodiment, a system to model a hardware specification includes a platform (106) arranged to receive an input data stream and transmit an output data stream. The system also includes a source (102) for a streaming application adapted to provide the input data stream at a source data rate, a destination (104) for the streaming application adapted to consume the output data stream at a destination data rate, and a data channel (110) coupling the platform and a computer (108). The computer uses the hardware specification to generate intermediate data streams, which, in turn, are used to streamline the modeling for the platform.
    Type: Application
    Filed: December 2, 2005
    Publication date: July 8, 2010
    Applicant: NXP B.V.
    Inventors: Timothy Allen Pontius, Gregory E. Ehmann, Robert L. Payne
  • Patent number: 7586401
    Abstract: A theft-prevention and tracking system and method for semi truck trailers or other vehicles. One or more status indicators, such as location, indication of unauthorized tampering, disconnection of the trailer from the truck, etc. communicate an alarm to a remote monitoring and dispatch center. A stolen vehicle can be remotely stopped at the command and control of the remote monitoring and dispatch center. Upon occurrence of a predetermined condition, such as stopping and blowing off the air from the brake system, the vehicle's brakes remain locked until entry of an authorization code or otherwise receiving authorization to proceed from the remote monitoring and dispatch center.
    Type: Grant
    Filed: February 17, 2006
    Date of Patent: September 8, 2009
    Inventor: Robert L. Payne
  • Publication number: 20080157942
    Abstract: A theft-prevention and tracking system and method for semi truck trailers or other vehicles. One or more status indicators, such as location, indication of unauthorized tampering, disconnection of the trailer from the truck, etc. communicate an alarm to a remote monitoring and dispatch center. A stolen vehicle can be remotely stopped at the command and control of the remote monitoring and dispatch center. Upon occurrence of a predetermined condition, such as stopping and blowing off the air from the brake system, the vehicle's brakes remain locked until entry of an authorization code or otherwise receiving authorization to proceed from the remote monitoring and dispatch center.
    Type: Application
    Filed: February 17, 2006
    Publication date: July 3, 2008
    Inventor: Robert L. Payne
  • Patent number: 7187741
    Abstract: A method and arrangement of passing data from a source clock domain to a non-synchronous receive clock domain are provided. A first processing circuit, located in the source clock domain, links write-address information with the data, and a clock generator generates a transmit clock signal in the source clock domain synchronous with a source clock. The first processing circuit transmits the clock signal and the data with the linked write-address information to a second processing circuit in the receive clock domain. In the receive clock domain, the second processing circuit writes the data at an address designating a storage element corresponding to the linked write-address information. The second processing circuit clocks the data into the storage element synchronous with the accompanying transmit clock signal responsive to a write enable signal from the source clock domain, and reads the data out of the storage element synchronous with a receive domain clock.
    Type: Grant
    Filed: October 31, 2001
    Date of Patent: March 6, 2007
    Assignee: NXP B.V.
    Inventors: Timothy Pontius, Robert L. Payne, David R. Evoy
  • Patent number: 6996106
    Abstract: A communication protocol provides high-speed transfers of parallel data between an origination end and a destination end. The protocol involves regularly transmitting data from the origination end to the destination end, including transmitting idle data from the origination end when the destination end is busy and during periods when no commands, data or statuses are pending. When the destination end is not busy, data is sent from the origination end to the destination end by: sequentially transferring read or write commands and, according to a write protocol, pending write data; and transmitting idle packets during periods when no commands are pending.
    Type: Grant
    Filed: November 29, 2001
    Date of Patent: February 7, 2006
    Assignee: Koninklijke Philips Electronics N.V.
    Inventors: Robert L. Payne, David R. Evoy, Timothy Pontius, George Ellis Spatz
  • Publication number: 20030099238
    Abstract: A communication protocol provides high-speed transfers of parallel data between an origination end and a destination end. The protocol involves regularly transmitting data from the origination end to the destination end, including transmitting idle data from the origination end when the destination end is busy and during periods when no commands, data or statuses are pending. When the destination end is not busy, data is sent from the origination end to the destination end by: sequentially transferring read or write commands and, according to a write protocol, pending write data; and transmitting idle packets during periods when no commands are pending.
    Type: Application
    Filed: November 29, 2001
    Publication date: May 29, 2003
    Applicant: Koninklijke Philips Electronics N.V.
    Inventors: Robert L. Payne, David R. Evoy, Timothy A. Pontius, George Ellis Spatz
  • Patent number: 6338158
    Abstract: Testing and validation of custom IC designs is performed using standard ICs. Highly complex integrated circuits, instead of being designed at the gates and flops level, are typically designed using standardized cell libraries that allow for widespread, systematic design reuse. Such libraries may include Functional System Blocks, or FSBs (sometimes referred to as ASIC cores), and Application Specific Standard Parts (ASSPs). ASSPs are designs that are or were once realized as stand-alone parts, but that may also be embedded into larger designs (“embedded ASSPs”). Instead of a conventional software model, testing and validation is performed using a hardware model of a custom integrated circuit. The hardware model may be a breadboard system that is decomposed into three levels of functionality: ASSPs, FSBs and “glue logic”ASSPs are typically 500K gates or more and may be realized as separate ICs. FSBs are typically 50K gates or less.
    Type: Grant
    Filed: October 31, 1997
    Date of Patent: January 8, 2002
    Assignee: VLSI Technology, Inc.
    Inventor: Robert L. Payne
  • Patent number: 6057598
    Abstract: The present invention provides methods and apparatus capable of efficiently combining a logic circuit die with a memory circuit die in a single integrated circuit device capable of supporting memory intensive applications, such as 3-dimensional graphics rendering, encryption and signal processing. The logic circuit die is produced independently with a logic circuit fabrication process that optimizes the logic circuit's performance and reduces costs, and the memory circuit die, which may contain a large memory circuit, can be produced independently with a memory circuit fabrication process that optimizes the memory circuit's performance and reduces costs. The circuit dies are attached directly together in a flip-chip fashion to create a unitary integrated circuit assembly having a high-performance, low impedance, wide-word interface.
    Type: Grant
    Filed: January 31, 1997
    Date of Patent: May 2, 2000
    Assignee: VLSI Technology, Inc.
    Inventors: Robert L. Payne, Herbert Reiter
  • Patent number: 6037669
    Abstract: A semiconductor die assembly of this invention includes a lead system in which the leads are arranged in a radial pattern. That is, in a group of leads associated with a single side of a semiconductor die, leads which are furthest from the middle are most angled from the perpendicular. The semiconductor die includes an outer row of bond pads which are located proximate to the edge of the semiconductor die and an inner row of bond pads, parallel to the first row and located toward the interior of the semiconductor die surface. In one embodiment, one of the rows of bond pads is regularly spaced, while the other row of bond pads is variably spaced.
    Type: Grant
    Filed: November 1, 1996
    Date of Patent: March 14, 2000
    Assignee: VLSI Technology, Inc.
    Inventors: William K. Shu, Robert L. Payne
  • Patent number: 5959905
    Abstract: Repair cells for performing metal-only functional repairs in a cell-based circuit layout design are described. The repair cells include a gate array under layer made-up of a group of uncommitted (not interconnected) transistors. A cluster of cells can be placed within the cell-based design in various locations and can be coupled together to form logic function elements. The repair cells can be added to cell-based designs during the metalization processing steps so as to repair/change the cell-based design's function. Furthermore, repair cells can be used as feedthrough cells to facilitate routing in the cell-based circuit layout. In this case, feedthrough cells having gate array underlayers may be arranged in columns or are placed in strategic spots within the layout to facilitate routing.
    Type: Grant
    Filed: October 31, 1997
    Date of Patent: September 28, 1999
    Assignee: VLSI Technology, Inc.
    Inventor: Robert L. Payne
  • Patent number: 5936880
    Abstract: A static, in-circuit programmable memory device is provided where the storage element employed is a bi-layer programmable resistor. A specialized programming and readout circuit is provided for each storage element, allowing a known word-line/bit-line memory architecture (commonly used with fuse type memories) to be adapted to a memory element that conducts in both of two different states. The programming and readout circuit may take the form of a merged bipolar/FET device. A bipolar transistor is used for programming and also provides a diode action to prevent sneak path currents from flowing when a storage element is not selected. The bipolar transistor may be a parasitic bipolar transistor. An FET is used for readout. Storage elements are paired, one storage element of each pair functioning as a reference element.
    Type: Grant
    Filed: November 13, 1997
    Date of Patent: August 10, 1999
    Assignee: VLSI Technology, Inc.
    Inventor: Robert L. Payne
  • Patent number: 5923608
    Abstract: A scalable N-port memory device using as a building block a dual-port memory device core. The dual-port memory has two ports each of which can either serve as a read or a write port. The resulting N-port memory device, besides allowing for design reuse, offers speed, density and cost advantages over conventional N-port memory devices. For example, to realize a 1K word by 128 bit register file memory device having two write ports and either five or six read ports, three dual-port memory device cores are placed in parallel with one another. Each core has separate parallel (dual) read ports. Two write ports are shared in common among all of the cores. The cores are designed to operate at 2X speed, i.e., twice the desired speed of the N-port memory device. A "cycle" at the N-port memory device is composed of two cycles of the underlying 2X speed devices, typically a read cycle followed by a write cycle.
    Type: Grant
    Filed: October 31, 1997
    Date of Patent: July 13, 1999
    Assignee: VLSI Technology, Inc.
    Inventor: Robert L. Payne
  • Patent number: 5446445
    Abstract: A mobile detection system for detecting a fire, gas leak, intruder, or other abnormal condition in a house or an office, and for alerting a central monitor, fire station, police station, or an occupant who is away from the house or office. The mobile detection system comprises a self-propelled movable robot having sensors located thereon. A monitor receives signals from the robot and alerts an authorized user accordingly. An automatic communication control unit includes a telephone transmitting unit for automatically calling an appropriate party in response to a signal from the robot and transmits commands to the robot from an authorized calling party. A radio frequency remote controller for remotely controls the robot. The robot is specifically capable of navigating throughout a house or an office while using its sensors to detect abnormal conditions.
    Type: Grant
    Filed: February 18, 1993
    Date of Patent: August 29, 1995
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: John W. Bloomfield, Rudi A. Bischoff, Robert L. Payne, Scott B. Wagner, Kim Sang-Gweon, Kim Tae-Sik, Kim Ji-Hyun, Jeong Joon-Young, Yoo Chang-Hyun, Dong-II Shin
  • Patent number: 4321561
    Abstract: An oscillator circuit is disclosed using a capacitive voltage divider, the circuit being integratable in a monolithic integrated circuit chip. Currents are switched into and out of that one of the capacitors in the divider which is connected through inverters to the other capacitor in a feedback loop. Switching of the currents is controlled in another feedback loop involving a further inverter.
    Type: Grant
    Filed: September 28, 1979
    Date of Patent: March 23, 1982
    Assignee: Honeywell Inc.
    Inventors: Robert L. Payne, Thomas R. Reinke
  • Patent number: 4310990
    Abstract: A structure made from tubular elements which interfit to form a plural compartment hydroponic unit. The upper compartment is filled with inert root medium, houses a fluid dispensing unit, and contains slits which communicate with the lower compartment which constitutes a resevoir. The tubular housings are substantially sealingly interconnected. The lower compartment contains a nutrient inlet provision which communicates via a manifold housed in the lower compartment with the interior of the upper compartment. The lower compartment also contains a drain provision.
    Type: Grant
    Filed: May 6, 1980
    Date of Patent: January 19, 1982
    Inventor: Robert L. Payne