Patents by Inventor Robert L. Reay
Robert L. Reay has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 7920016Abstract: A testing procedure may determine whether a monolithic voltage reference device meets a temperature drift specification. A first non-room temperature output voltage of the monolithic voltage reference device may be measured while the monolithic voltage reference device is at a first non-room temperature which is substantially different than room temperature. First non-room temperature information may be stored in a memory within the monolithic voltage reference device which is a function of the first non-room temperature output voltage. A second non-room temperature output voltage of the monolithic voltage reference device may be measured while the monolithic voltage reference device is at a second non-room temperature which is substantially different than the room temperature and the first non-room temperature. Second non-room temperature information may be stored in the memory without destroying the first non-room temperature information which is a function of the second non-room temperature output voltage.Type: GrantFiled: May 29, 2009Date of Patent: April 5, 2011Assignee: Linear Technology CorporationInventors: Michael B. Anderson, Tahir M. Hasoon, Brendan J. Whelan, J. Spencer Wright, Robert L. Reay
-
Publication number: 20100301923Abstract: A testing procedure may determine whether a monolithic voltage reference device meets a temperature drift specification. A first non-room temperature output voltage of the monolithic voltage reference device may be measured while the monolithic voltage reference device is at a first non-room temperature which is substantially different than room temperature. First non-room temperature information may be stored in a memory within the monolithic voltage reference device which is a function of the first non-room temperature output voltage. A second non-room temperature output voltage of the monolithic voltage reference device may be measured while the monolithic voltage reference device is at a second non-room temperature which is substantially different than the room temperature and the first non-room temperature. Second non-room temperature information may be stored in the memory without destroying the first non-room temperature information which is a function of the second non-room temperature output voltage.Type: ApplicationFiled: May 29, 2009Publication date: December 2, 2010Applicant: LINEAR TECHNOLOGY CORPORATIONInventors: Michael B. Anderson, Tahir M. Hasoon, Brendan J. Whelan, J. Spencer Wright, Robert L. Reay
-
Patent number: 7239251Abstract: Electronic devices, and methods, for transmitting, transferring and/or conveying a multi-bit digital signal as a voltage signal via a single pin. Devices and methods according to the invention substantially reduce the pin count of a device because inputting of a multi-bit digital signal preferably does not use more than one input pin. In addition, the speed of transmission is improved because the multi-bit digital signal is transmitted as a voltage signal substantially at one time as opposed to serially.Type: GrantFiled: September 9, 2005Date of Patent: July 3, 2007Assignee: Linear Technology CorporationInventors: David M Dwelley, Robert L Reay
-
Patent number: 7119714Abstract: Electronic devices, and methods, for transmitting, transferring and/or conveying a multi-bit digital signal as a voltage signal via a single pin. Devices and methods according to the invention substantially reduce the pin count of a device because inputting of a multi-bit digital signal preferably does not use more than one input pin. In addition, the speed of transmission is improved because the multi-bit digital signal is transmitted as a voltage signal substantially at one time as opposed to serially.Type: GrantFiled: September 9, 2005Date of Patent: October 10, 2006Assignee: Linear Technology CorporationInventors: David M Dwelley, Robert L Reay
-
Patent number: 7032051Abstract: Circuits and methods for interconnecting a live backplane and at least one I/O card are provided. This invention provides interconnection circuitry that utilizes buffer circuitry to connect the data and clock busses of the backplane to the data and clock busses of the I/O card in a “hot-swappable” fashion. Buffer circuitry also isolates the capacitance associated with the backplane from the capacitance associated with the I/O card. For example, when at least one signal is driven from the backplane to the I/O card, the signal need only overcome the capacitance associate with the backplane. Conversely, when at least one signal is driven from the I/O card to the backplane, the signal need only overcome the capacitance associated with the I/O card. Hence, this capacitive isolation facilitates signal propagation between the backplane and the I/O card.Type: GrantFiled: December 11, 2001Date of Patent: April 18, 2006Assignee: Linear Technology Corp.Inventors: Robert L. Reay, John H. Ziegler
-
Patent number: 6967591Abstract: Electronic devices, and methods, for transmitting, transferring and/or conveying a multi-bit digital signal as a voltage signal via a single pin. Devices and methods according to the invention substantially reduce the pin count of a device because inputting of a multi-bit digital signal preferably does not use more than one input pin. In addition, the speed of transmission is improved because the multi-bit digital signal is transmitted as a voltage signal substantially at one time as opposed to serially.Type: GrantFiled: April 15, 2002Date of Patent: November 22, 2005Assignee: Linear Technology CorporationInventors: David M. Dwelley, Robert L. Reay
-
Patent number: 6819094Abstract: Methods and circuits implementing a constant-current/constant-voltage circuit architecture are provided. The methods and circuits preferably provide a charging system that provides current to a load using a fixed current until the load is charged. When the load is charged, the methods and circuits preferably provide a variable current to the load in order to maintain the voltage level across the load. This variable current varies according to the voltage across the load. In one embodiment of the invention, a constant power current may also be used as one of the load charging currents. The constant power current may act as a limit on the charging circuit's power output.Type: GrantFiled: November 17, 2003Date of Patent: November 16, 2004Assignee: Linear Technology CorporationInventors: Trevor W. Barcelo, Robert L. Reay, David M. Dwelley
-
Publication number: 20040100243Abstract: Methods and circuits implementing a constant-current/constant-voltage circuit architecture are provided. The methods and circuits preferably provide a charging system that provides current to a load using a fixed current until the load is charged. When the load is charged, the methods and circuits preferably provide a variable current to the load in order to maintain the voltage level across the load. This variable current varies according to the voltage across the load. In one embodiment of the invention, a constant power current may also be used as one of the load charging currents. The constant power current may act as a limit on the charging circuit's power output.Type: ApplicationFiled: November 17, 2003Publication date: May 27, 2004Applicant: Linear Technology CorporationInventors: Trevor W. Barcelo, Robert L. Reay, David M. Dwelley
-
Patent number: 6700364Abstract: Methods and circuits implementing a constant-current/constant-voltage circuit architecture are provided. The methods and circuits preferably provide a charging system that provides current to a load using a fixed current until the load is charged. When the load is charged, the methods and circuits preferably provide a variable current to the load in order to maintain the voltage level across the load. This variable current varies according to the voltage across the load. In one embodiment of the invention, a constant power current may also be used as one of the load charging currents. The constant power current may act as a limit on the charging circuit's power output.Type: GrantFiled: May 21, 2003Date of Patent: March 2, 2004Assignee: Linear Technology CorporationInventors: Trevor W. Barcelo, Robert L. Reay, David M. Dwelley
-
Publication number: 20030197497Abstract: Methods and circuits implementing a constant-current/constant-voltage circuit architecture are provided. The methods and circuits preferably provide a charging system that provides current to a load using a fixed current until the load is charged. When the load is charged, the methods and circuits preferably provide a variable current to the load in order to maintain the voltage level across the load. This variable current varies according to the voltage across the load. In one embodiment of the invention, a constant power current may also be used as one of the load charging currents. The constant power current may act as a limit on the charging circuit's power output.Type: ApplicationFiled: May 21, 2003Publication date: October 23, 2003Applicant: Linear Technology CorporationInventors: Trevor W. Barcelo, Robert L. Reay, David M. Dwelley
-
Patent number: 6570372Abstract: Methods and circuits implementing a constant-current/constant-voltage circuit architecture are provided. The methods and circuits preferably provide a charging system that provides current to a load using a fixed current until the load is charged. When the load is charged, the methods and circuits preferably provide a variable current to the load in order to maintain the voltage level across the load. This variable current varies according to the voltage across the load. In one embodiment of the invention, a constant power current may also be used as one of the load charging currents. The constant power current may act as a limit on the charging circuit's power output.Type: GrantFiled: March 27, 2002Date of Patent: May 27, 2003Assignee: Linear Technology CorporationInventors: Trevor W. Barcelo, Robert L. Reay, David M. Dwelley
-
Patent number: 6522118Abstract: Methods and circuits implementing a constant-current/constant-voltage circuit architecture are provided. The methods and circuits preferably provide a charging system that provides current to a load using a fixed current until the load is charged. When the load is charged, the methods and circuits preferably provide a variable current to the load in order to maintain the voltage level across the load. This variable current varies according to the voltage across the load. In one embodiment of the invention, a constant power current may also be used as one of the load charging currents. The constant power current may act as a limit on the charging circuit's power output.Type: GrantFiled: April 18, 2001Date of Patent: February 18, 2003Assignee: Linear Technology CorporationInventors: Trevor W. Barcelo, Robert L. Reay, David M. Dwelley
-
Publication number: 20020153871Abstract: Methods and circuits implementing a constant-current/constant-voltage circuit architecture are provided. The methods and circuits preferably provide a charging system that provides current to a load using a fixed current until the load is charged. When the load is charged, the methods and circuits preferably provide a variable current to the load in order to maintain the voltage level across the load. This variable current varies according to the voltage across the load. In one embodiment of the invention, a constant power current may also be used as one of the load charging currents. The constant power current may act as a limit on the charging circuit's power output.Type: ApplicationFiled: March 27, 2002Publication date: October 24, 2002Applicant: Linear TechnologyInventors: Trevor W. Barcelo, Robert L. Reay, David M. Dwelley
-
Publication number: 20020091887Abstract: Circuits and methods for interconnecting a live backplane and at least one I/O card are provided. This invention provides interconnection circuitry that utilizes buffer circuitry to connect the data and clock busses of the backplane to the data and clock busses of the I/O card in a “hot-swappable” fashion. Buffer circuitry also isolates the capacitance associated with the backplane from the capacitance associated with the I/O card. For example, when at least one signal is driven from the backplane to the I/O card, the signal need only overcome the capacitance associate with the backplane. Conversely, when at least one signal is driven from the I/O card to the backplane, the signal need only overcome the capacitance associated with the I/O card. Hence, this capacitive isolation facilitates signal propagation between the backplane and the I/O card.Type: ApplicationFiled: December 11, 2001Publication date: July 11, 2002Inventors: Robert L. Reay, John H. Ziegler
-
Patent number: 5945728Abstract: A capacitor is provided including first and second electrodes formed from portions of the lead frame structure used in conventional integrated circuit packaging. The electrodes are encapsulated with dielectric molding material which provides dielectric insulation between the electrodes. A low power capacitively-coupled digital isolator circuit is also provided. The circuit employs a pair of the lead frame capacitors of the present invention and includes differential driver and receiver circuits. The receiver can also include an optional filter for increasing noise and glitch immunity.Type: GrantFiled: February 27, 1997Date of Patent: August 31, 1999Assignee: Linear Technology CorporationInventors: Robert C. Dobkin, Robert L. Reay
-
Patent number: 5926358Abstract: A capacitor is provided including first and second electrodes formed from portions of the lead frame structure used in conventional integrated circuit packaging. The electrodes are encapsulated with dielectric molding material which provides dielectric insulation between the electrodes. A low power capacitively-coupled digital isolator circuit is also provided. The circuit employs a pair of the lead frame capacitors of the present invention and includes differential driver and receiver circuits. The receiver can also include an optional filter for increasing noise and glitch immunity.Type: GrantFiled: March 8, 1995Date of Patent: July 20, 1999Assignee: Linear Technology CorporationInventors: Robert C. Dobkin, Robert L. Reay
-
Patent number: 5714955Abstract: Serial analog-to-digital converters (ADC) in which power down and power up modes are activated by two dual-purpose input signals are provided. The ADCs of the invention eliminate the need for a dedicated power down input line as found on typical serial ADCs. When commanded to do so, the ADC enters into one of two power down modes, NAP or SLEEP. In NAP mode, only those portions of the ADC circuit which consume current and which are capable of waking up almost instantaneously are powered down. In SLEEP mode, the entire ADC circuit is powered down. When commanded to do so, the ADC enters into a power up mode, applying current to every portion of the ADC circuit. Wake-up from the NAP mode takes place almost instantaneously. Wake-up from the SLEEP mode requires additional time. From either mode, a signal is generated when the ADC conversion circuit, which preferably includes a reference voltage generator, has stabilized sufficiently for the ADC to perform analog-to-digital conversion.Type: GrantFiled: June 7, 1995Date of Patent: February 3, 1998Assignee: Linear Technology CorporationInventors: Robert L. Reay, Yang-Long Teo, William C. Rempfer
-
Patent number: 5650357Abstract: A capacitor is provided including first and second electrodes formed from portions of the lead frame structure used in conventional integrated circuit packaging. The electrodes are encapsulated with dielectric molding material which provides dielectric insulation between the electrodes. A low power capacitively-coupled digital isolator circuit is also provided. The circuit employs a pair of the lead frame capacitors of the present invention and includes differential driver and receiver circuits. The receiver can also include an optional filter for increasing noise and glitch immunity.Type: GrantFiled: March 8, 1995Date of Patent: July 22, 1997Assignee: Linear Technology CorporationInventors: Robert C. Dobkin, Robert L. Reay
-
Patent number: 5589709Abstract: A capacitor is provided including first and second electrodes formed from portions of the lead frame structure used in conventional integrated circuit packaging. The electrodes are encapsulated with dielectric molding material which provides dielectric insulation between the electrodes. A low power capacitively-coupled digital isolator circuit is also provided. The circuit employs a pair of the lead frame capacitors of the present invention and includes differential driver and receiver circuits. The receiver can also include an optional filter for increasing noise and glitch immunity.Type: GrantFiled: March 8, 1995Date of Patent: December 31, 1996Assignee: Linear Technology Inc.Inventors: Robert C. Dobkin, Robert L. Reay
-
Patent number: RE35221Abstract: The high impedance state of a tri-state CMOS transistor output circuit is enhanced by serially connecting first and second Schottky diodes with the P-channel transistor and the N-channel transistor whereby in the high impedance state reverse bias of the substrate/source-drain diodes of the two transistors is prevented when the output of the circuit is taken beyond the supply voltage potentials of the output circuit.Type: GrantFiled: May 13, 1993Date of Patent: April 30, 1996Assignee: Linear Technology CorporationInventor: Robert L. Reay