Abstract: A power amplifier provided with overload protection responsive to the impedance of a load falling below a threshold value having a pair of power output devices connected to the load and driven through a balanced operational amplifier and transistor couplers. The operational amplifier has opposed voltage supply inputs, and each is connected through a first resistor to a voltage source and to the load through a pair of diodes connected in series opposition and a second resistor, and the junction between the diodes is connected to the base of one of the transistor couplers. A fault condition causes current to flow through the diodes lowering the potentials of the voltage supply inputs and the bias on the transistor couplers.

Abstract: A noise reduction system including a signal path (34) between an input terminal (12) and an output terminal (36), a voltage control amplifier (38) and a control path (40) between the input terminal and the voltage control amplifier is disclosed. A nonlinear element such as a voltage squarer (32) is in the controlled path. In one arrangement, the control path also includes a signal level detector (22), a one-pole high pass filter (16) and a direct current level shifter (26). A precision diode (30) is interposed in the control path between the direct current level shifter and the signal squarer. One form of the noise reduction system includes a voltage-controlled low pass filter (20) interposed in the signal path between the input terminal and the voltage-controlled amplifier. A weighing control path (46) provides the control signal for the voltage-controlled low pass filter. A two-pole high pass filter (18) followed by a level sensor (48) is interposed in the weighting control path.

Abstract: A kinescope driver stage includes an input amplifier transistor arranged in a cascode amplifier configuration with an output amplifier transistor. The low impedance emitter electrode of the input transistor is coupled to a reference potential via an impedance network. Degenerative feedback is provided from the impedance network to input circuits of the input amplifier.

Abstract: A dynamic range expander which substantially limits the amount of positive expansion without affecting the amount of negative expansion is disclosed. In one arrangement, gain reduction in the amplitude of the output signal is increased when the amplitude of the input signal decreases toward or becomes less than the noise level present in the input signal. The dynamic range expander includes a detector (24) for sensing the amplitude of the input signal and providing a variable DC signal related to the amplitude of the input signal, a control signal generator (30) and an amplifier (34) for amplifying the input signal by a gain variable responsively to the output of the control signal generator. The control signal generator includes a time averager (50) and a summer (40) for providing a second variable DC signal related to the sum of the detector output and the time averaged detector output.

Abstract: A focussing system for a camera tube in which the nominal magnitude of the focus tube voltage and focus coil current are predetermined and in which incremental changes in the focus voltage result in square-root proportional incremental changes in the focus current. Alternatively, incremental changes in focus current result in changes in the focus voltage which are proportional to the square of the current changes by which they are caused.

Abstract: In this relaxation oscillator first and second electrically controlled constant current generators are used to provide proportionately related first and second currents to first and second terminals, respectively, between which the timing capacitor is connected. Set-reset, or R-S, flip-flop means is set and reset by the voltage at the first and second terminals, respectively, departing in a first sense from the voltage at a reference voltage bus by a predetermined amount. First switching means responds to the R-S flip-flop reset condition to complete a connection of the first terminal to the reference voltage bus and responds to the R-S flip-flop set condition to interrupt that connection. Second switching means responds to the R-S flip-flop set condition to complete a connection of the second terminal to the reference voltage bus and responds to the R-S flip-flop reset condition to interrupt that connection.

Abstract: A simplified bootstrap deflection circuit includes a sawtooth capacitor with one end grounded. First and second serially connected resistors provide charging current to form a ramp voltage across the capacitor. The noninverting input of an amplifier is coupled to receive the ramp. The amplifier output is coupled to a deflection winding and current sensing resistor. A feedback path couples the current sensing resistor to the inverting input terminal. A resistor is coupled to the inverting input terminal and to a reference potential. A bootstrap capacitor couples sawtooth feedback voltage at the inverting input terminal to the junction of the first and second capacitors for producing a constant voltage across the second resistor for linearizing the ramp. The feedback path includes a series variable resistor which acts as a centering control.

Abstract: A commercial automatic-iris lens assembly responds to the average value of the video signals applied to its control input. For use in industrial and surveillance camera applications, the video signals applied to the control input of the automatic iris from an image sensor are passed through a controllable-gain amplifier. The gain of the amplifier is controlled in response to the peak value of the video signals produced by the image sensor to provide an effective peak responding iris.

Abstract: A synchronizing signal for a television camera includes a count-down system by which standard horizontal and vertical synchronizing signals are generated and added to the video signals being produced. In order to allow the camera to be synchronized to a nonstandard source of synchronizing signals such as a television game, computer with TV display, another television camera or a video recorder for allowing split-screen applications, the count-down system is phase-locked to the external sync portions of the external sync signals. Thus, standard sync signals are produced by the camera at a rate controlled by a nonstandard sync source. In order to prevent slewing of the system during the vertical equalizing or synchronizing portions of the external sync signals, the phase-lock loop which controls the frequency of the count-down system is inhibited during at least the vertical synchronizing and equalizing pulse portions of the external synchronizing signals.

Abstract: CCD imagers of the field transfer type which include a surface channel A register and a buried channel C register.