Abstract: A fault tolerant processing system including a prediction RAM employs a Lock Step Compare routine. The method developed allows the processing system to recover from single event upsets. In initialization, the branch prediction RAM is set to a known value. An engineering balance is achieved by adding logic to detect a branch RAM error and incurring the delay of re-initializing the entire RAM only when a RAM error has been detected.

Abstract: An improved checkpoint retry mechanism is disclosed which automatically updates checkpoint addresses to enable the retry of instruction sequences for shorter segments of recently executed code, in response to the detection of an error since the passage of the current checkpoint. It does this by updating three different types of checkpoint addresses, a first checkpoint address for the instruction which follows a memory write or I/O write operation, a second type checkpoint address for the first instruction in an interrupt service routine, and a third type checkpoint address for the first instruction in an interrupted routine following an interrupt event. The resulting checkpoint retry mechanism is more efficient and faster because it adaptively updates the checkpoint address to reduce the size of code segments which must be reexecuted during retry operations. The invention operates to avoid memory corruption and erroneous I/O outputs during retry operations and protects from erroneous retry sequences.