Patents by Inventor Robert L. Shuler
Robert L. Shuler has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20110012638Abstract: A device is disclosed in one embodiment that has multiple identical sets of programmable functional elements, programmable routing resources, and majority voters that correct errors. The voters accept a mode input for a redundancy mode and a split mode. In the redundancy mode, the programmable functional elements are identical and are programmed identically so the voters produce an output corresponding to the majority of inputs that agree. In a split mode, each voter selects a particular programmable functional element output as the output of the voter. Therefore, in the split mode, the programmable functional elements can perform different functions, operate independently, and/or be connected together to process different parts of the same problem.Type: ApplicationFiled: July 14, 2009Publication date: January 20, 2011Inventor: Robert L. Shuler, JR.
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Patent number: 7859292Abstract: A device is disclosed in one embodiment that has multiple identical sets of programmable functional elements, programmable routing resources, and majority voters that correct errors. The voters accept a mode input for a redundancy mode and a split mode. In the redundancy mode, the programmable functional elements are identical and are programmed identically so the voters produce an output corresponding to the majority of inputs that agree. In a split mode, each voter selects a particular programmable functional element output as the output of the voter. Therefore, in the split mode, the programmable functional elements can perform different functions, operate independently, and/or be connected together to process different parts of the same problem.Type: GrantFiled: July 14, 2009Date of Patent: December 28, 2010Assignee: United States of America as represented by the Administrator of the National Aeronautics and Space AdministrationInventor: Robert L. Shuler, Jr.
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Patent number: 6943621Abstract: A method and apparatus for an acquisition system includes a plurality of sensor input signal lines. At least one of the plurality of sensor input signal lines operatively connects to at least one of a plurality of amplifier circuits. At least one of the plurality of amplifier circuits operatively connects to at least one of a plurality of filter circuits.Type: GrantFiled: May 21, 2003Date of Patent: September 13, 2005Assignee: The United States of America as represented by the Administrator of the National Aeronautics and Space AdministrationInventor: Robert L. Shuler, Jr.
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Patent number: 6943619Abstract: A method and apparatus is described that filters an electrical signal. The filtering uses a capacitor multiplier circuit where the capacitor multiplier circuit uses at least one amplifier circuit and at least one capacitor. A filtered electrical signal results from a direct connection from an output of the at least one amplifier circuit.Type: GrantFiled: May 21, 2003Date of Patent: September 13, 2005Assignee: The United States of America as represented by the Administrator of the National Aeronautics and Space AdministrationInventor: Robert L. Shuler, Jr.
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Patent number: 6492857Abstract: A delay circuit includes a first network having an input and an output node, a second network having an input and an output, the input of the second network being coupled to the output node of the first network. The first network and the second network are configured such that: a glitch at the input to the first network having a length of approximately one-half of a standard glitch time or less does not cause the voltage at the output of the second network to cross a threshold, a glitch at the input to the first network having a length of between approximately one-half and two standard glitch times causes the voltage at the output of the second network to cross the threshold for less than the length of the glitch, and a glitch at the input to the first network having a length of greater than approximately two standard glitch times causes the voltage at the output of the second network to cross the threshold for approximately the time of the glitch.Type: GrantFiled: April 20, 2001Date of Patent: December 10, 2002Assignee: The United States of America as represented by the United States National Aeronautics and Space AdministrationInventor: Robert L. Shuler, Jr.
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Patent number: 6377097Abstract: A delay circuit includes a first network having an input and an output node, a second network having an input and an output, the input of the second network being coupled to the output node of the first network. The first network and the second network are configured such that: a glitch at the input to the first network having a length of approximately one-half of a standard glitch time or less does not cause the voltage at the output of the second network to cross a threshold, a glitch at the input to the first network having a length of between approximately one-half and two standard glitch times causes the voltage at the output of the second network to cross the threshold for less than the length of the glitch, and a glitch at the input to the first network having a length of greater than approximately two standard glitch times causes the voltage at the output of the second network to cross the threshold for approximately the time of the glitch.Type: GrantFiled: March 13, 2000Date of Patent: April 23, 2002Assignee: The United States of America as represented by the Administrator of the National Aeronautics and Space AdministrationInventor: Robert L. Shuler, Jr.
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Publication number: 20010028268Abstract: A delay circuit includes a first network having an input and an output node, a second network having an input and an output, the input of the second network being coupled to the output node of the first network. The first network and the second network are configured such that: a glitch at the input to the first network having a length of approximately one-half of a standard glitch time or less does not cause the voltage at the output of the second network to cross a threshold, a glitch at the input to the first network having a length of between approximately one-half and two standard glitch times causes the voltage at the output of the second network to cross the threshold for less than the length of the glitch, and a glitch at the input to the first network having a length of greater than approximately two standard glitch times causes the voltage at the output of the second network to cross the threshold for approximately the time of the glitch.Type: ApplicationFiled: April 20, 2001Publication date: October 11, 2001Applicant: National Aeronautics & SpaceInventor: Robert L. Shuler
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Publication number: 20010028269Abstract: A delay circuit includes a first network having an input and an output node, a second network having an input and an output, the input of the second network being coupled to the output node of the first network. The first network and the second network are configured such that: a glitch at the input to the first network having a length of approximately one-half of a standard glitch time or less does not cause the voltage at the output of the second network to cross a threshold, a glitch at the input to the first network having a length of between approximately one-half and two standard glitch times causes the voltage at the output of the second network to cross the threshold for less than the length of the glitch, and a glitch at the input to the first network having a length of greater than approximately two standard glitch times causes the voltage at the output of the second network to cross the threshold for approximately the time of the glitch.Type: ApplicationFiled: April 20, 2001Publication date: October 11, 2001Applicant: Government of the United States of America, National Aeronautics & SpaceInventor: Robert L. Shuler
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Patent number: 4912629Abstract: In a list processing system, small reference counters are maintained in conjunction with memory cells for the purpose of identifying memory cells that become available for re-use. The counters are updated as references to the cells are created and destroyed, and when a counter of a cell is decremented to logical zero the cell is immediately returned to a list of free cells. In those cases where a counter must be incremented beyond the maximum value that can be represented in a small counter, the cell is restructured so that the additional reference count can be represented. The restructuring involves allocating an additional cell, distributing counter, tag, and pointer information among the two cells, and linking both cells appropriately into the existing list structure.Type: GrantFiled: June 26, 1986Date of Patent: March 27, 1990Assignee: The United States of America as represented by the Administrator of the National Aeronautics and Space AdministrationInventor: Robert L. Shuler, Jr.