Patents by Inventor Robert L. Shuler

Robert L. Shuler has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method and apparatus for reducing the vulnerability of latches to single event upsets
    Publication number: 20010028269
    Abstract: A delay circuit includes a first network having an input and an output node, a second network having an input and an output, the input of the second network being coupled to the output node of the first network. The first network and the second network are configured such that: a glitch at the input to the first network having a length of approximately one-half of a standard glitch time or less does not cause the voltage at the output of the second network to cross a threshold, a glitch at the input to the first network having a length of between approximately one-half and two standard glitch times causes the voltage at the output of the second network to cross the threshold for less than the length of the glitch, and a glitch at the input to the first network having a length of greater than approximately two standard glitch times causes the voltage at the output of the second network to cross the threshold for approximately the time of the glitch.
    Type: Application
    Filed: April 20, 2001
    Publication date: October 11, 2001
    Applicant: Government of the United States of America, National Aeronautics & Space
    Inventor: Robert L. Shuler
  • Method and apparatus for reducing the vulnerability of latches to single event upsets
    Publication number: 20010028268
    Abstract: A delay circuit includes a first network having an input and an output node, a second network having an input and an output, the input of the second network being coupled to the output node of the first network. The first network and the second network are configured such that: a glitch at the input to the first network having a length of approximately one-half of a standard glitch time or less does not cause the voltage at the output of the second network to cross a threshold, a glitch at the input to the first network having a length of between approximately one-half and two standard glitch times causes the voltage at the output of the second network to cross the threshold for less than the length of the glitch, and a glitch at the input to the first network having a length of greater than approximately two standard glitch times causes the voltage at the output of the second network to cross the threshold for approximately the time of the glitch.
    Type: Application
    Filed: April 20, 2001
    Publication date: October 11, 2001
    Applicant: National Aeronautics & Space
    Inventor: Robert L. Shuler