Abstract: A communications concentrator and message multiplexer featuring direct access from the communications adapters to main memory via direct memory access means which eliminates the usual scanner or polling facility in a concentrator or multiplexer is described. A control microprocessor manages the allocation of memory, the conversion of message protocols and the servicing of interrupts to a plurality of port interface adapter microprocessors. The interface adapter microprocessors directly set up and control the DMA operation instead of having the DMA operation controlled by the control processor. One of the port adapters serves as a service adapter over a dedicated interface allowing a remote disgnostician access to internal registers in the control processor system, access to a dedicated read only storage for servicing, and logical interface to the main control processor for the purpose of entering instructions and directing functional operations to test each component of the system.

Abstract: A technique for regulating the transmission of messages initiated simultaneously by a plurality of nodes of a network, in which clock intervals are established for the network, a sequence of digital values is included in each message and is transmitted to the medium at the rate of one digital value per clock interval, the sequences included in messages that are initiated at the same time by more than one node are transmitted in the same sequence of clock intervals, the presence on the medium of a selected digital value during any clock interval in which a node is transmitting a different digital value within the sequence of a message is detected, and the transmission of the message is interrupted by the node upon such detection, without corrupting another node's transmission.