Patents by Inventor Robert L. Toutant

Robert L. Toutant has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method of joining a chip on a substrate
    Patent number: 9393633
    Abstract: A method and apparatus for making chip assemblies is disclosed that prevent or reduce the cracking and delamination of ultra low-k dielectrics in the back-end-of-line in Si chips that can occur during the chip assembly process. The method and apparatus apply pressure to the top and bottom surfaces of a substrate during the chip bonding process so that the bending and warping of the assembled modules are reduced. The reduced bending and warping prevent or reduce the cracking and delamination of ultra low-k dielectrics.
    Type: Grant
    Filed: September 1, 2009
    Date of Patent: July 19, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Pascal P Blais, Paul F Fortier, Kang-Wook Lee, Jae-Woong Nah, Soojae Park, Robert L Toutant, Alain A Warren
  • METHOD OF JOINING A CHIP ON A SUBSTRATE
    Publication number: 20120292375
    Abstract: A method and apparatus for making chip assemblies is disclosed that prevent or reduce the cracking and delamination of ultra low-k dielectrics in the back-end-of-line in Si chips that can occur during the chip assembly process. The method and apparatus apply pressure to the top and bottom surfaces of a substrate during the chip bonding process so that the bending and warping of the assembled modules are reduced. The reduced bending and warping prevent or reduce the cracking and delamination of ultra low-k dielectrics.
    Type: Application
    Filed: August 3, 2012
    Publication date: November 22, 2012
    Applicant: International Business Machines Corporation
    Inventors: Pascal P. Blais, Paul F. Fortier, Kang-Wook Lee, Jae-Woong Nah, Soojae Park, Robert L. Toutant, Alain A. Warren
  • METHOD OF JOINING A CHIP ON A SUBSTRATE
    Publication number: 20110049221
    Abstract: A method and apparatus for making chip assemblies is disclosed that prevent or reduce the cracking and delamination of ultra low-k dielectrics in the back-end-of-line in Si chips that can occur during the chip assembly process. The method and apparatus apply pressure to the top and bottom surfaces of a substrate during the chip bonding process so that the bending and warping of the assembled modules are reduced. The reduced bending and warping prevent or reduce the cracking and delamination of ultra low-k dielectrics.
    Type: Application
    Filed: September 1, 2009
    Publication date: March 3, 2011
    Applicant: International Business Machines Corporation
    Inventors: Pascal P. Blais, Paul F. Fortier, Kang-Wook Lee, Jae-Woong Nah, Soojae Park, Robert L. Toutant, Alain A. Warren
  • Control of flux by ink stop line in chip joining
    Patent number: 6904673
    Abstract: Ink jet printing apparatus is employed to form a non-polar ink stop line around a chip site on the polar surface of an organic laminate substrate. The non-polar ink stop line acts to confine polar liquid flux from spreading after application of the flux to the chip site prior to chip joining. Excessive flux spreading results in insufficient flux being present at the chip site for the formation of good electrical connections during solder reflow upon chip joining.
    Type: Grant
    Filed: September 24, 2002
    Date of Patent: June 14, 2005
    Assignee: International Business Machines Corporation
    Inventors: Claude Blais, Julie Nadeau Filteau, Pierre M. Langevin, Robert L. Toutant, Alain Warren