Patents by Inventor Robert Lamoon

Robert Lamoon has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Stress relief solutions on WLCSP large/bulk copper plane design
    Patent number: 10083926
    Abstract: A wafer level chip scale package is described. At least one redistribution layer is connected to a wafer through an opening through a first polymer layer to a metal pad on a top surface of the wafer wherein the redistribution layer has a roughened top surface and wherein holes are formed through the at least one redistribution layer in an area where the redistribution layer has an area exceeding 0.2 mm2. At least one UBM layer contacts the at least one redistribution layer through an opening in a second polymer layer wherein the second polymer layer contacts the first polymer layer within the holes promoting cohesion between the first and second polymer layers and wherein the roughened top surface promotes adhesion between the at least one redistribution layer and the second polymer layer.
    Type: Grant
    Filed: December 13, 2017
    Date of Patent: September 25, 2018
    Assignee: Dialog Semiconductor (UK) Limited
    Inventors: Ian Kent, Rajesh Subraya Aiyandra, Jesus Mennen Belonio, Jr., Habeeb Mohiuddin Mohammed, Domingo Jr. Maggay, Robert Lamoon, Ernesto Gutierrez, III