Patents by Inventor Robert Lee Maziasz

Robert Lee Maziasz has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7124385
    Abstract: A method for generating an integrated circuit layout is disclosed. One embodiment includes receiving an integrated circuit netlist describing a plurality of transistors and a plurality of conductors for interconnecting the plurality of transistors, each of the plurality of transistors having a width in a layout corresponding to the integrated circuit netlist. More than one of the plurality of transistors are determined to be the widest transistors, all having the same width. One of the widest transistors is folded to produce a folded transistor that is electrically equivalent to the widest transistor. The folded transistor has at least two fingers, each finger having a smaller width than the width of the widest transistors. A fold solution for the layout having the one folded transistor is created.
    Type: Grant
    Filed: September 8, 2003
    Date of Patent: October 17, 2006
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Patrick James McGuinness, Robert Lee Maziasz, Andrei Vladimirovitch Zinchenko, Vladimir Pavlovich Rozenfeld, Michael Viacheslavovich Golikov, Alexander Mikhailovich Marchenko
  • Publication number: 20040078768
    Abstract: A method for generating an integrated circuit layout is disclosed. One embodiment includes receiving an integrated circuit netlist describing a plurality of transistors and a plurality of conductors for interconnecting the plurality of transistors, each of the plurality of transistors having a width in a layout corresponding to the integrated circuit netlist. More than one of the plurality of transistors are determined to be the widest transistors, all having the same width. One of the widest transistors is folded to produce a folded transistor that is electrically equivalent to the widest transistor. The folded transistor has at least two fingers, each finger having a smaller width than the width of the widest transistors. A fold solution for the layout having the one folded transistor is created.
    Type: Application
    Filed: September 8, 2003
    Publication date: April 22, 2004
    Inventors: Patrick James McGuinness, Robert Lee Maziasz, Andrei Vladimirovitch Zinchenko, Vladimir Pavlovich Rozenfeld, Michael Viacheslavovich Golikov, Alexander Mikhailovich Marchenko